/* * linux/arch/alpha/kernel/sys_dp264.c * * Copyright (C) 1995 David A Rusling * Copyright (C) 1996, 1999 Jay A Estabrook * Copyright (C) 1998, 1999 Richard Henderson * * Modified by Christopher C. Chimelis, 2001 to * add support for the addition of Shark to the * Tsunami family. * * Code supporting the DP264 (EV6+TSUNAMI). */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "proto.h" #include "irq_impl.h" #include "pci_impl.h" #include "machvec_impl.h" /* Note mask bit is true for ENABLED irqs. */ static unsigned long cached_irq_mask; /* dp264 boards handle at max four CPUs */ static unsigned long cpu_irq_affinity[4] = { 0UL, 0UL, 0UL, 0UL }; DEFINE_SPINLOCK(dp264_irq_lock); static void tsunami_update_irq_hw(unsigned long mask) { register tsunami_cchip *cchip = TSUNAMI_cchip; unsigned long isa_enable = 1UL << 55; register int bcpu = boot_cpuid; #ifdef CONFIG_SMP volatile unsigned long *dim0, *dim1, *dim2, *dim3; unsigned long mask0, mask1, mask2, mask3, dummy; mask &= ~isa_enable; mask0 = mask & cpu_irq_affinity[0]; mask1 = mask & cpu_irq_affinity[1]; mask2 = mask & cpu_irq_affinity[2]; mask3 = mask & cpu_irq_affinity[3]; if (bcpu == 0) mask0 |= isa_enable; else if (bcpu == 1) mask1 |= isa_enable; else if (bcpu == 2) mask2 |= isa_enable; else mask3 |= isa_enable; dim0 = &cchip->dim0.csr; dim1 = &cchip->dim1.csr; dim2 = &cchip->dim2.csr; dim3 = &cchip->dim3.csr; if (!cpu_possible(0)) dim0 = &dummy; if (!cpu_possible(1)) dim1 = &dummy; if (!cpu_possible(2)) dim2 = &dummy; if (!cpu_possible(3)) dim3 = &dummy; *dim0 = mask0; *dim1 = mask1; *dim2 = mask2; *dim3 = mask3; mb(); *dim0; *dim1; *dim2; *dim3; #else volatile unsigned long *dimB; if (bcpu == 0) dimB = &cchip->dim0.csr; else if (bcpu == 1) dimB = &cchip->dim1.csr; else if (bcpu == 2) dimB = &cchip->dim2.csr; else dimB = &cchip->dim3.csr; *dimB = mask | isa_enable; mb(); *dimB; #endif } static void dp264_enable_irq(struct irq_data *d) { spin_lock(&dp264_irq_lock); cached_irq_mask |= 1UL << d->irq; tsunami_update_irq_hw(cached_irq_mask); spin_unlock(&dp264_irq_lock); } static void dp264_disable_irq(struct irq_data *d) { spin_lock(&dp264_irq_lock); cached_irq_mask &= ~(1UL << d->irq); tsunami_update_irq_hw(cached_irq_mask); spin_unlock(&dp264_irq_lock); } static void clipper_enable_irq(struct irq_data *d) { spin_lock(&dp264_irq_lock); cached_irq_mask |= 1UL << (d->irq - 16); tsunami_update_irq_hw(cached_irq_mask); spin_unlock(&dp264_irq_lock); } static void clipper_disable_irq(struct irq_data *d) { spin_lock(&dp264_irq_lock); cached_irq_mask &= ~(1UL << (d->irq - 16)); tsunami_update_irq_hw(cached_irq_mask); spin_unlock(&dp264_irq_lock); } static void cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity) { int cpu; for (cpu = 0; cpu < 4; cpu++) { unsigned long aff = cpu_irq_affinity[cpu]; if (cpumask_test_cpu(cpu, &affinity)) aff |= 1UL << irq; else aff &= ~(1UL << irq); cpu_irq_affinity[cpu] = aff; } } static int dp264_set_affinity(struct irq_data *d, const struct cpumask *affinity, bool force) { spin_lock(&dp264_irq_lock); cpu_set_irq_affinity(d->irq, *affinity); tsunami_update_irq_hw(cached_irq_mask); spin_unlock(&dp264_irq_lock); return 0; } static int clipper_set_affinity(struct irq_data *d, const struct cpumask *affinity, bool force) { spin_lock(&dp264_irq_lock); cpu_set_irq_affinity(d->irq - 16, *affinity); tsunami_update_irq_hw(cached_irq_mask); spin_unlock(&dp264_irq_lock); return 0; } static struct irq_chip dp264_irq_type = { .name = "DP264", .irq_unmask = dp264_enable_irq, .irq_mask = dp264_disable_irq, .irq_mask_ack = dp264_disable_irq, .irq_set_affinity = dp264_set_affinity, }; static struct irq_chip clipper_irq_type = { .name = "CLIPPER", .irq_unmask = clipper_enable_irq, .irq_mask = clipper_disable_irq, .irq_mask_ack = clipper_disable_irq, .irq_set_affinity = clipper_set_affinity, }; static void dp264_device_interrupt(unsigned long vector) { #if 1 printk("dp264_device_interrupt: NOT IMPLEMENTED YET!!\n"); #else unsigned long pld; unsigned int i; /* Read the interrupt summary register of TSUNAMI */ pld = TSUNAMI_cchip->dir0.csr; /* * Now for every possible bit set, work through them and call * the appropriate interrupt handler. */ while (pld) { i = ffz(~pld); pld &= pld - 1; /* clear least bit set */ if (i == 55) isa_device_interrupt(vector); else handle_irq(16 + i); #if 0 TSUNAMI_cchip->dir0.csr = 1UL << i; mb(); tmp = TSUNAMI_cchip->dir0.csr; #endif } #endif } static void dp264_srm_device_interrupt(unsigned long vector) { int irq; irq = (vector - 0x800) >> 4; /* * The SRM console reports PCI interrupts with a vector calculated by: * * 0x900 + (0x10 * DRIR-bit) * * So bit 16 shows up as IRQ 32, etc. * * On DP264/BRICK/MONET, we adjust it down by 16 because at least * that many of the low order bits of the DRIR are not used, and * so we don't count them. */ if (irq >= 32) irq -= 16; handle_irq(irq); } static void clipper_srm_device_interrupt(unsigned long vector) { int irq; irq = (vector - 0x800) >> 4; /* * The SRM console reports PCI interrupts with a vector calculated by: * * 0x900 + (0x10 * DRIR-bit) * * So bit 16 shows up as IRQ 32, etc. * * CLIPPER uses bits 8-47 for PCI interrupts, so we do not need * to scale down the vector reported, we just use it. * * Eg IRQ 24 is DRIR bit 8, etc, etc */ handle_irq(irq); } static void __init init_tsunami_irqs(struct irq_chip * ops, int imin, int imax) { long i; for (i = imin; i <= imax; ++i) { irq_set_chip_and_handler(i, ops, handle_level_irq); irq_set_status_flags(i, IRQ_LEVEL); } } static void __init dp264_init_irq(void) { outb(0, DMA1_RESET_REG);