#ifndef _M68K_DMA_H #define _M68K_DMA_H 1 #ifdef CONFIG_COLDFIRE /* * ColdFire DMA Model: * ColdFire DMA supports two forms of DMA: Single and Dual address. Single * address mode emits a source address, and expects that the device will either * pick up the data (DMA READ) or source data (DMA WRITE). This implies that * the device will place data on the correct byte(s) of the data bus, as the * memory transactions are always 32 bits. This implies that only 32 bit * devices will find single mode transfers useful. Dual address DMA mode * performs two cycles: source read and destination write. ColdFire will * align the data so that the device will always get the correct bytes, thus * is useful for 8 and 16 bit devices. This is the mode that is supported * below. * * AUG/22/2000 : added support for 32-bit Dual-Address-Mode (K) 2000 * Oliver Kamphenkel (O.Kamphenkel@tu-bs.de) * * AUG/25/2000 : addad support for 8, 16 and 32-bit Single-Address-Mode (K)2000 * Oliver Kamphenkel (O.Kamphenkel@tu-bs.de) * * APR/18/2002 : added proper support for MCF5272 DMA controller. * Arthur Shipkowski (art@videon-central.com) */ #include #include #include /* * Set number of channels of DMA on ColdFire for different implementations. */ #if defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) || \ defined(CONFIG_M523x) || defined(CONFIG_M527x) || \ defined(CONFIG_M528x) || defined(CONFIG_M525x) #define MAX_M68K_DMA_CHANNELS 4 #elif defined(CONFIG_M5272) #define MAX_M68K_DMA_CHANNELS 1 #elif defined(CONFIG_M532x) #define MAX_M68K_DMA_CHANNELS 0 #else #define MAX_M68K_DMA_CHANNELS 2 #endif extern unsigned int dma_base_addr[MAX_M68K_DMA_CHANNELS]; extern unsigned int dma_device_address[MAX_M68K_DMA_CHANNELS]; #if !defined(CONFIG_M5272) #define DMA_MODE_WRITE_BIT 0x01 /* Memory/IO to IO/Memory select */ #define DMA_MODE_WORD_BIT 0x02 /* 8 or 16 bit transfers */ #define DMA_MODE_LONG_BIT 0x04 /* or 32 bit transfers */ #define DMA_MODE_SINGLE_BIT 0x08 /* single-address-mode */ /* I/O to memory, 8 bits, mode */ #define DMA_MODE_READ 0 /* memory to I/O, 8 bits, mode */ #define DMA_MODE_WRITE 1 /* I/O to memory, 16 bits, mode */ #define DMA_MODE_READ_WORD 2 /* memory to I/O, 16 bits, mode */ #define DMA_MODE_WRITE_WORD 3 /* I/O to memory, 32 bits, mode */ #define DMA_MODE_READ_LONG 4 /* memory to I/O, 32 bits, mode */ #define DMA_MODE_WRITE_LONG 5 /* I/O to memory, 8 bits, single-address-mode */ #define DMA_MODE_READ_SINGLE 8 /* memory to I/O, 8 bits, single-address-mode */ #define DMA_MODE_WRITE_SINGLE 9 /* I/O to memory, 16 bits, single-address-mode */ #define DMA_MODE_READ_WORD_SINGLE 10 /* memory to I/O, 16 bits, single-address-mode */ #define DMA_MODE_WRITE_WORD_SINGLE 11 /* I/O to memory, 32 bits, single-address-mode */ #define DMA_MODE_READ_LONG_SINGLE 12 /* memory to I/O, 32 bits, single-address-mode */ #define DMA_MODE_WRITE_LONG_SINGLE 13 #else /* CONFIG_M5272 is defined */ /* Source static-address mode */ #define DMA_MODE_SRC_SA_BIT 0x01 /* Two bits to select between all four modes */ #define DMA_MODE_SSIZE_MASK 0x06 /* Offset to shift bits in */ #define DMA_MODE_SSIZE_OFF 0x01 /* Destination static-address mode */ #define DMA_MODE_DES_SA_BIT 0x10 /* Two bits to select between all four modes */ #define DMA_MODE_DSIZE_MASK 0x60 /* Offset to shift bits in */ #define DMA_MODE_DSIZE_OFF 0x05 /* Size modifiers */ #define DMA_MODE_SIZE_LONG 0x00 #define DMA_MODE_SIZE_BYTE 0x01 #define DMA_MODE_SIZE_WORD 0x02 #define DMA_MODE_SIZE_LINE 0x03 /* * Aliases to help speed quick ports; these may be suboptimal, however. They * do not include the SINGLE mode modifiers since the MCF5272 does not have a * mode where the device is in control of its addressing. */ /* I/O to memory, 8 bits, mode */ #define DMA_MODE_READ ((DMA_MODE_SIZE_BYTE << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_BYTE << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT) /* memory to I/O, 8 bits, mode */ #define DMA_MODE_WRITE ((DMA_MODE_SIZE_BYTE << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_BYTE << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT) /* I/O to memory, 16 bits, mode */ #define DMA_MODE_READ_WORD ((DMA_MODE_SIZE_WORD << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_WORD << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT) /* memory to I/O, 16 bits, mode */ #define DMA_MODE_WRITE_WORD ((DMA_MODE_SIZE_WORD << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_WORD << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT) /* I/O to memory, 32 bits, mode */ #define DMA_MODE_READ_LONG ((DMA_MODE_SIZE_LONG << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_LONG << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT) /* memory to I/O, 32 bits, mode */ #define DMA_MODE_WRITE_LONG ((DMA_MODE_SIZE_LONG << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_LONG << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT) #endif /* !defined(CONFIG_M5272) */ #if !defined(CONFIG_M5272) /* enable/disable a specific DMA channel */ static __inline__ void enable_dma(unsigned int dmanr) { volatile unsigned short *dmawp; #ifdef DMA_DEBUG printk("enable_dma(dmanr=%d)\n", dmanr); #endif dmawp = (unsigned short *) dma_base_addr[dmanr]; dmawp[MCFDMA_DCR] |= MCFDMA_DCR_EEXT; } static __inline__ void disable_dma(unsigned int dmanr) { volatile unsigned short *dmawp; volatile unsigned char *dmapb; #ifdef DMA_DEBUG printk("disable_dma(dmanr=%d)\n", dmanr); #endif dmawp = (unsigned short *) dma_base_addr[dmanr]; dmapb = (unsigned char *) dma_base_addr[dmanr]; /* Turn off external requests, and stop any DMA in progress */ dmawp[MCFDMA_DCR] &= ~MCFDMA_DCR_EEXT; dmapb[MCFDMA_DSR] = MCFDMA_DSR_DONE; } /* * Clear the 'DMA Pointer Flip Flop'. * Write 0 for LSB/MSB, 1 for MSB/LSB access. * Use this once to initialize the FF to a known state. * After that, keep track of it. :-) * --- In order to do that, the DMA routines below should --- * --- only be used while interrupts are disabled! --- * * This is a NOP for ColdFire. Provide a stub for compatibility. */ static __inline__ void clear_dma_ff(unsigned int dmanr) { } /* set mode (above) for a specific DMA channel */ static __inline__ void set_dma_mode(unsigned int dmanr, char mode) { volatile unsigned char *dmabp; volatile unsigned short *dmawp; #ifdef DMA_DEBUG printk("set_dma_mode(dmanr=%d,mode=%d)\n", dmanr, mode); #endif dmabp = (unsigned char *) dma_base_addr[dmanr]; dmawp = (unsigned short *) dma_base_addr[dmanr]; /* Clear config errors */ dmabp[MCFDMA_DSR] = MCFDMA_DSR_DONE;