#ifndef _ASM_M32R_M32R_MP_FPGA_
#define _ASM_M32R_M32R_MP_FPGA_

/*
 * Renesas M32R-MP-FPGA
 *
 * Copyright (c) 2002  Hitoshi Yamamoto
 * Copyright (c) 2003, 2004  Renesas Technology Corp.
 */

/*
 * ========================================================
 * M32R-MP-FPGA Memory Map
 * ========================================================
 * 0x00000000 : Block#0 : 64[MB]
 *              0x03E00000 : SFR
 *                           0x03E00000 : reserved
 *                           0x03EF0000 : FPGA
 *                           0x03EF1000 : reserved
 *                           0x03EF4000 : CKM
 *                           0x03EF4000 : BSELC
 *                           0x03EF5000 : reserved
 *                           0x03EFC000 : MFT
 *                           0x03EFD000 : SIO
 *                           0x03EFE000 : reserved
 *                           0x03EFF000 : ICU
 *              0x03F00000 : Internal SRAM 64[KB]
 *              0x03F10000 : reserved
 * --------------------------------------------------------
 * 0x04000000 : Block#1 : 64[MB]
 *              0x04000000 : Debug board SRAM 4[MB]
 *              0x04400000 : reserved
 * --------------------------------------------------------
 * 0x08000000 : Block#2 : 64[MB]
 * --------------------------------------------------------
 * 0x0C000000 : Block#3 : 64[MB]
 * --------------------------------------------------------
 * 0x10000000 : Block#4 : 64[MB]
 * --------------------------------------------------------
 * 0x14000000 : Block#5 : 64[MB]
 * --------------------------------------------------------
 * 0x18000000 : Block#6 : 64[MB]
 * --------------------------------------------------------
 * 0x1C000000 : Block#7 : 64[MB]
 * --------------------------------------------------------
 * 0xFE000000 : TLB
 *              0xFE000000 : ITLB
 *              0xFE000080 : reserved
 *              0xFE000800 : DTLB
 *              0xFE000880 : reserved
 * --------------------------------------------------------
 * 0xFF000000 : System area
 *              0xFFFF0000 : MMU
 *              0xFFFF0030 : reserved
 *              0xFFFF8000 : Debug function
 *              0xFFFFA000 : reserved
 *              0xFFFFC000 : CPU control
 * 0xFFFFFFFF
 * ========================================================
 */

/*======================================================================*
 * Special Function Register
 *======================================================================*/
#define M32R_SFR_OFFSET  (0x00E00000)  /* 0x03E00000-0x03EFFFFF 1[MB] */

/*
 * FPGA registers.
 */
#define M32R_FPGA_TOP  (0x000F0000+M32R_SFR_OFFSET)

#define M32R_FPGA_NUM_OF_CPUS_PORTL  (0x00+M32R_FPGA_TOP)
#define M32R_FPGA_CPU_NAME0_PORTL    (0x10+M32R_FPGA_TOP)
#define M32R_FPGA_CPU_NAME1_PORTL    (0x14+M32R_FPGA_TOP)
#define M32R_FPGA_CPU_NAME2_PORTL    (0x18+M32R_FPGA_TOP)
#define M32R_FPGA_CPU_NAME3_PORTL    (0x1C+M32R_FPGA_TOP)
#define M32R_FPGA_MODEL_ID0_PORTL    (0x20+M32R_FPGA_TOP)
#define M32R_FPGA_MODEL_ID1_PORTL    (0x24+M32R_FPGA_TOP)