/* * linux/arch/arm/mach-omap1/clock_data.c * * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation * Written by Tuukka Tikkanen * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * To do: * - Clocks that are only available on some chips should be marked with the * chips that they are present on. */ #include #include #include #include #include #include /* for machine_is_* */ #include "soc.h" #include #include /* for OTG_BASE */ #include "iomap.h" #include "clock.h" #include "sram.h" /* Some ARM_IDLECT1 bit shifts - used in struct arm_idlect1_clk */ #define IDL_CLKOUT_ARM_SHIFT 12 #define IDLTIM_ARM_SHIFT 9 #define IDLAPI_ARM_SHIFT 8 #define IDLIF_ARM_SHIFT 6 #define IDLLB_ARM_SHIFT 4 /* undocumented? */ #define OMAP1510_IDLLCD_ARM_SHIFT 3 /* undocumented? */ #define IDLPER_ARM_SHIFT 2 #define IDLXORP_ARM_SHIFT 1 #define IDLWDT_ARM_SHIFT 0 /* Some MOD_CONF_CTRL_0 bit shifts - used in struct clk.enable_bit */ #define CONF_MOD_UART3_CLK_MODE_R 31 #define CONF_MOD_UART2_CLK_MODE_R 30 #define CONF_MOD_UART1_CLK_MODE_R 29 #define CONF_MOD_MMC_SD_CLK_REQ_R 23 #define CONF_MOD_MCBSP3_AUXON 20 /* Some MOD_CONF_CTRL_1 bit shifts - used in struct clk.enable_bit */ #define CONF_MOD_SOSSI_CLK_EN_R 16 /* Some OTG_SYSCON_2-specific bit fields */ #define OTG_SYSCON_2_UHOST_EN_SHIFT 8 /* Some SOFT_REQ_REG bit fields - used in struct clk.enable_bit */ #define SOFT_MMC2_DPLL_REQ_SHIFT 13 #define SOFT_MMC_DPLL_REQ_SHIFT 12 #define SOFT_UART3_DPLL_REQ_SHIFT 11 #define SOFT_UART2_DPLL_REQ_SHIFT 10 #define SOFT_UART1_DPLL_REQ_SHIFT 9 #define SOFT_USB_OTG_DPLL_REQ_SHIFT 8 #define SOFT_CAM_DPLL_REQ_SHIFT 7 #define SOFT_COM_MCKO_REQ_SHIFT 6 #define SOFT_PERIPH_REQ_SHIFT 5 /* sys_ck gate for UART2 ? */ #define USB_REQ_EN_SHIFT 4 #define SOFT_USB_REQ_SHIFT 3 /* sys_ck gate for USB host? */ #define SOFT_SDW_REQ_SHIFT 2 /* sys_ck gate for Bluetooth? */ #define SOFT_COM_REQ_SHIFT 1 /* sys_ck gate for com proc? */ #define SOFT_DPLL_REQ_SHIFT 0 /* * Omap1 clocks */ static struct clk ck_ref = { .name = "ck_ref", .ops = &clkops_null, .rate = 12000000, }; static struct clk ck_dpll1 = { .name = "ck_dpll1", .ops = &clkops_null, .parent = &ck_ref, }; /* * FIXME: This clock seems to be necessary but no-one has asked for its * activation. [ FIX: SoSSI, SSR ] */ static struct arm_idlect1_clk ck_dpll1out = { .clk = { .name = "ck_dpll1out", .ops = &clkops_generic, .parent = &ck_dpll1, .flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT | ENABLE_ON_INIT, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), .enable_bit = EN_CKOUT_ARM, .recalc = &followparent_recalc, }, .idlect_shift = IDL_CLKOUT_ARM_SHIFT, }; static struct clk sossi_ck = { .name = "ck_sossi", .ops = &clkops_generic, .parent = &ck_dpll1out.clk, .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT, .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1), .enable_bit = CONF_MOD_SOSSI_CLK_EN_R, .recalc = &omap1_sossi_recalc, .set_rate = &omap1_set_sossi_rate, }; static struct clk arm_ck = { .name = "arm_ck", .ops = &clkops_null, .parent = &ck_dpll1, .rate_offset = CKCTL_ARMDIV_OFFSET, .recalc = &omap1_ckctl_recalc, .round_rate = omap1_clk_round_rate_ckctl_arm, .set_rate = omap1_clk_set_rate_ckctl_arm, }; static struct arm_idlect1_clk armper_ck = { .clk = { .name = "armper_ck", .ops = &clkops_generic, .parent = &ck_dpll1, .flags = CLOCK_IDLE_CONTROL, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), .enable_bit = EN_PERCK, .rate_offset = CKCTL_PERDIV_OFFSET, .recalc = &omap1_ckctl_recalc, .round_rate = omap1_clk_round_rate_ckctl_arm, .set_rate = omap1_clk_set_rate_ckctl_arm, }, .idlect_shift = IDLPER_ARM_SHIFT, }; /* * FIXME: This clock seems to be necessary but no-one has asked for its * activation. [ GPIO code for 1510 ] */ static struct clk arm_gpio_ck = { .name = "ick", .ops = &clkops_generic, .parent = &ck_dpll1, .flags = ENABLE_ON_INIT, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), .enable_bit = EN_GPIOCK, .recalc = &followparent_recalc, }; static struct arm_idlect1_clk armxor_ck = { .clk = { .name = "armxor_ck", .ops = &clkops_generic, .parent = &ck_ref, .flags = CLOCK_IDLE_CONTROL, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), .enable_bit = EN_XORPCK, .recalc = &followparent_recalc, }, .idlect_shift = IDLXORP_ARM_SHIFT, }; static struct arm_idlect1_clk armtim_ck = { .clk = { .name = "armtim_ck", .ops = &clkops_generic, .parent = &ck_ref, .flags = CLOCK_IDLE_CONTROL, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), .enable_bit = EN_TIMCK, .recalc = &followparent_recalc, }, .idlect_shift = IDLTIM_ARM_SHIFT, }; static struct arm_idlect1_clk armwdt_ck = { .clk = { .name = "armwdt_ck", .ops = &clkops_generic, .parent = &ck_ref, .flags = CLOCK_IDLE_CONTROL, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), .enable_bit = EN_WDTCK, .fixed_div = 14, .recalc = &omap_fixed_divisor_recalc, }, .idlect_shift = IDLWDT_ARM_SHIFT, }; static struct clk arminth_ck16xx = { .name = "arminth_ck", .ops = &clkops_null, .parent = &arm_ck, .recalc = &followparent_recalc, /* Note: On 16xx the frequency can be divided by 2 by programming * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1 * * 1510 version is in TC clocks. */ }; static struct clk dsp_ck = { .name = "dsp_ck", .ops = &clkops_generic, .parent = &ck_dpll1, .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL), .enable_bit = EN_DSPCK, .rate_offset = CKCTL_DSPDIV_OFFSET, .recalc = &omap1_ckctl_recalc, .round_rate = omap1_clk_round_rate_ckctl_arm, .set_rate = omap1_clk_set_rate_ckctl_arm, }; static struct clk dspmmu_ck = { .name = "dspmmu_ck", .ops = &clkops_null, .parent = &ck_dpll1, .rate_offset = CKCTL_DSPMMUDIV_OFFSET, .recalc = &omap1_ckctl_recalc, .round_rate = omap1_clk_round_rate_ckctl_arm, .set_rate = omap1_clk_set_rate_ckctl_arm, }; static struct clk dspper_ck = { .name = "dspper_ck", .ops = &clkops_dspck, .parent = &ck_dpll1, .enable_reg = DSP_IDLECT2, .enable_bit = EN_PERCK, .rate_offset = CKCTL_PERDIV_OFFSET, .recalc = &omap1_ckctl_recalc_dsp_domain, .round_rate = omap1_clk_round_rate_ckctl_arm, .set_rate = &omap1_clk_set_rate_dsp_domain, }; static struct clk dspxor_ck = { .name = "dspxor_ck", .ops = &clkops_dspck, .parent = &ck_ref, .enable_reg = DSP_IDLECT2, .enable_bit = EN_XORPCK, .recalc = &followparent_recalc, }; static struct clk dsptim_ck = { .name = "dsptim_ck", .ops = &clkops_dspck, .parent = &ck_ref, .enable_reg = DSP_IDLECT2, .enable_bit = EN_DSPTIMCK, .recalc = &followparent_recalc, }; static struct arm_idlect1_clk tc_ck = { .clk = { .name = "tc_ck", .ops = &clkops_null, .parent = &ck_dpll1, .flags = CLOCK_IDLE_CONTROL, .rate_offset = CKCTL_TCDIV_OFFSET, .recalc = &omap1_ckctl_recalc, .round_rate = omap1_clk_round_rate_ckctl_arm, .set_rate = omap1_clk_set_rate_ckctl_arm, }, .idlect_shift = IDLIF_ARM_SHIFT, }; static struct clk arminth_ck1510 = { .name = "arminth_ck", .ops = &clkops_null, .parent = &tc_ck.clk, .recalc = &followparent_recalc, /* Note: On 1510 the frequency follows TC_CK * * 16xx version is in MPU clocks. */ }; static struct clk tipb_ck = { /* No-idle controlled by "tc_ck" */ .name = "tipb_ck", .ops = &clkops_null, .parent = &tc_ck.clk, .recalc = &followparent_recalc, }; static struct clk l3_ocpi_ck = { /* No-idle controlled by "tc_ck" */ .name = "l3_ocpi_ck", .ops = &clkops_generic, .parent = &tc_ck.clk, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), .enable_bit = EN_OCPI_CK, .recalc = &followparent_recalc, }; static struct clk tc1_ck = { .name = "tc1_ck", .ops = &clkops_generic, .parent = &tc_ck.clk, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), .enable_bit = EN_TC1_CK, .recalc = &followparent_recalc, }; /* * FIXME: This clock seems to be necessary but no-one has asked for its * activation. [ pm.c (SRAM), CCP, Camera ] */ static struct clk tc2_ck = { .name = "tc2_ck", .ops = &clkops_generic, .parent = &tc_ck.clk, .flags = ENABLE_ON_INIT, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), .enable_bit = EN_TC2_CK, .recalc = &followparent_recalc, }; static struct clk dma_ck = { /* No-idle controlled by "tc_ck" */ .name = "dma_ck", .ops = &clkops_null, .parent = &tc_ck.clk, .recalc = &followparent_recalc, }; static struct clk dma_lcdfree_ck = { .name = "dma_lcdfree_ck", .ops = &clkops_null, .parent = &tc_ck.clk, .recalc = &followparent_recalc, }; static struct arm_idlect1_clk api_ck = { .clk = { .name = "api_ck", .ops = &clkops_generic, .parent = &tc_ck.clk, .flags = CLOCK_IDLE_CONTROL, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), .enable_bit = EN_APICK, .recalc = &followparent_recalc, }, .idlect_shift = IDLAPI_ARM_SHIFT, }; static struct arm_idlect1_clk lb_ck = { .clk = { .name = "lb_ck", .ops = &clkops_generic, .parent = &tc_ck.clk, .flags = CLOCK_IDLE_CONTROL, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), .enable_bit = EN_LBCK, .recalc = &followparent_recalc, }, .idlect_shift = IDLLB_ARM_SHIFT, }; static struct clk rhea1_ck = { .name = "rhea1_ck", .ops = &clkops_null, .parent = &tc_ck.clk, .recalc = &followparent_recalc, }; static struct clk rhea2_ck = { .name = "rhea2_ck", .ops = &clkops_null, .parent = &tc_ck.clk, .recalc = &followparent_recalc, }; static struct clk lcd_ck_16xx = { .name = "lcd_ck", .ops = &clkops_generic, .parent = &ck_dpll1, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), .enable_bit = EN_LCDCK, .rate_offset = CKCTL_LCDDIV_OFFSET, .recalc = &omap1_ckctl_recalc, .round_rate = omap1_clk_round_rate_ckctl_arm, .set_rate = omap1_clk_set_rate_ckctl_arm, }; static struct arm_idlect1_clk lcd_ck_1510 = { .clk = { .name = "lcd_ck", .ops = &clkops_generic, .parent = &ck_dpll1, .flags = CLOCK_IDLE_CONTROL, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), .enable_bit = EN_LCDCK, .rate_offset = CKCTL_LCDDIV_OFFSET, .recalc = &omap1_ckctl_recalc, .round_rate = omap1_clk_round_rate_ckctl_arm, .set_rate = omap1_clk_set_rate_ckctl_arm, }, .idlect_shift = OMAP1510_IDLLCD_ARM_SHIFT, }; /* * XXX The enable_bit here is misused - it simply switches between 12MHz * and 48MHz. Reimplement with clksel. *