/*
 * MT regs definitions, follows on from mipsregs.h
 * Copyright (C) 2004 - 2005 MIPS Technologies, Inc.  All rights reserved.
 * Elizabeth Clarke et. al.
 *
 */
#ifndef _ASM_MIPSMTREGS_H
#define _ASM_MIPSMTREGS_H

#include <asm/mipsregs.h>
#include <asm/war.h>

#ifndef __ASSEMBLY__

/*
 * C macros
 */

#define read_c0_mvpcontrol()		__read_32bit_c0_register($0, 1)
#define write_c0_mvpcontrol(val)	__write_32bit_c0_register($0, 1, val)

#define read_c0_mvpconf0()		__read_32bit_c0_register($0, 2)
#define read_c0_mvpconf1()		__read_32bit_c0_register($0, 3)

#define read_c0_vpecontrol()		__read_32bit_c0_register($1, 1)
#define write_c0_vpecontrol(val)	__write_32bit_c0_register($1, 1, val)

#define read_c0_vpeconf0()		__read_32bit_c0_register($1, 2)
#define write_c0_vpeconf0(val)		__write_32bit_c0_register($1, 2, val)

#define read_c0_vpeconf1()		__read_32bit_c0_register($1, 3)
#define write_c0_vpeconf1(val)		__write_32bit_c0_register($1, 3, val)

#define read_c0_tcstatus()		__read_32bit_c0_register($2, 1)
#define write_c0_tcstatus(val)		__write_32bit_c0_register($2, 1, val)

#define read_c0_tcbind()		__read_32bit_c0_register($2, 2)

#define read_c0_tccontext()		__read_32bit_c0_register($2, 5)
#define write_c0_tccontext(val)		__write_32bit_c0_register($2, 5, val)

#else /* Assembly */
/*
 * Macros for use in assembly language code
 */

#define CP0_MVPCONTROL		$0, 1
#define CP0_MVPCONF0		$0, 2
#define CP0_MVPCONF1		$0, 3
#define CP0_VPECONTROL		$1, 1
#define CP0_VPECONF0		$1, 2
#define CP0_VPECONF1		$1, 3
#define CP0_YQMASK		$1, 4
#define CP0_VPESCHEDULE		$1, 5
#define CP0_VPESCHEFBK		$1, 6
#define CP0_TCSTATUS		$2, 1
#define CP0_TCBIND		$2, 2
#define CP0_TCRESTART		$2, 3
#define CP0_TCHALT		$2, 4
#define CP0_TCCONTEXT		$2, 5
#define CP0_TCSCHEDULE		$2, 6
#define CP0_TCSCHEFBK		$2, 7
#define CP0_SRSCONF0		$6, 1
#define CP0_SRSCONF1		$6, 2
#define CP0_SRSCONF2		$6, 3
#define CP0_SRSCONF3		$6, 4
#define CP0_SRSCONF4		$6, 5

#endif

/* MVPControl fields */
#define MVPCONTROL_EVP		(_ULCAST_(1))

#define MVPCONTROL_VPC_SHIFT	1
#define MVPCONTROL_VPC		(_ULCAST_(1) << MVPCONTROL_VPC_SHIFT)

#define MVPCONTROL_STLB_SHIFT	2
#define MVPCONTROL_STLB		(_ULCAST_(1) << MVPCONTROL_STLB_SHIFT)


/* MVPConf0 fields */
#define MVPCONF0_PTC_SHIFT	0
#define MVPCONF0_PTC		( _ULCAST_(0xff))
#define MVPCONF0_PVPE_SHIFT	10
#define MVPCONF0_PVPE		( _ULCAST_(0xf) << MVPCONF0_PVPE_SHIFT)
#define MVPCONF0_TCA_SHIFT	15
#define MVPCONF0_TCA		( _ULCAST_(1) << MVPCONF0_TCA_SHIFT)