/* * * arch/arm/mach-u300/include/mach/syscon.h * * * Copyright (C) 2008-2012 ST-Ericsson AB * * Author: Rickard Andersson */ #ifndef __MACH_SYSCON_H #define __MACH_SYSCON_H /* * All register defines for SYSCON registers that concerns individual * block clocks and reset lines are registered here. This is because * we don't want any other file to try to fool around with this stuff. */ /* APP side SYSCON registers */ /* TODO: this is incomplete. Add all from asic_syscon_map.h eventually. */ /* CLK Control Register 16bit (R/W) */ #define U300_SYSCON_CCR (0x0000) #define U300_SYSCON_CCR_I2S1_USE_VCXO (0x0040) #define U300_SYSCON_CCR_I2S0_USE_VCXO (0x0020) #define U300_SYSCON_CCR_TURN_VCXO_ON (0x0008) #define U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK (0x0007) #define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER (0x04) #define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW (0x03) #define U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE (0x02) #define U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH (0x01) #define U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST (0x00) /* CLK Status Register 16bit (R/W) */ #define U300_SYSCON_CSR (0x0004) #define U300_SYSCON_CSR_PLL208_LOCK_IND (0x0002) #define U300_SYSCON_CSR_PLL13_LOCK_IND (0x0001) /* Reset lines for SLOW devices 16bit (R/W) */ #define U300_SYSCON_RSR (0x0014) #define U300_SYSCON_RSR_PPM_RESET_EN (0x0200) #define U300_SYSCON_RSR_ACC_TMR_RESET_EN (0x0100) #define U300_SYSCON_RSR_APP_TMR_RESET_EN (0x0080) #define U300_SYSCON_RSR_RTC_RESET_EN (0x0040) #define U300_SYSCON_RSR_KEYPAD_RESET_EN (0x0020) #define U300_SYSCON_RSR_GPIO_RESET_EN (0x0010) #define U300_SYSCON_RSR_EH_RESET_EN (0x0008) #define U300_SYSCON_RSR_BTR_RESET_EN (0x0004) #define U300_SYSCON_RSR_UART_RESET_EN (0x0002) #define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN (0x0001) /* Reset lines for FAST devices 16bit (R/W) */ #define U300_SYSCON_RFR (0x0018) #define U300_SYSCON_RFR_UART1_RESET_ENABLE (0x0080) #define U300_SYSCON_RFR_SPI_RESET_ENABLE (0x0040) #define U300_SYSCON_RFR_MMC_RESET_ENABLE (0x0020) #define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE (0x0010) #define U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE (0x0008) #define U300_SYSCON_RFR_I2C1_RESET_ENABLE (0x0004) #define U300_SYSCON_RFR_I2C0_RESET_ENABLE (0x0002) #define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE (0x0001) /* Reset lines for the rest of the peripherals 16bit (R/W) */ #define U300_SYSCON_RRR (0x001c) #define U300_SYSCON_RRR_CDS_RESET_EN (0x4000) #define U300_SYSCON_RRR_ISP_RESET_EN (0x2000) #define U300_SYSCON_RRR_INTCON_RESET_EN (0x1000) #define U300_SYSCON_RRR_MSPRO_RESET_EN (0x0800) #define U300_SYSCON_RRR_XGAM_RESET_EN (0x0100) #define U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN (0x0080) #define U300_SYSCON_RRR_NANDIF_RESET_EN (0x0040) #define U300_SYSCON_RRR_EMIF_RESET_EN (0x0020) #define U300_SYSCON_RRR_DMAC_RESET_EN (0x0010)