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@@ -0,0 +1,89 @@
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+/*
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+ * linux/arch/alpha/kernel/core_mcpcia.c
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+ *
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+ * Based on code written by David A Rusling (david.rusling@reo.mts.dec.com).
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+ *
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+ * Code common to all MCbus-PCI Adaptor core logic chipsets
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+ */
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+
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+#define __EXTERN_INLINE inline
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+#include <asm/io.h>
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+#include <asm/core_mcpcia.h>
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+#undef __EXTERN_INLINE
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+
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+#include <linux/types.h>
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+#include <linux/pci.h>
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+#include <linux/sched.h>
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+#include <linux/init.h>
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+#include <linux/delay.h>
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+
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+#include <asm/ptrace.h>
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+
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+#include "proto.h"
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+#include "pci_impl.h"
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+
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+/*
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+ * NOTE: Herein lie back-to-back mb instructions. They are magic.
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+ * One plausible explanation is that the i/o controller does not properly
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+ * handle the system transaction. Another involves timing. Ho hum.
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+ */
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+
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+/*
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+ * BIOS32-style PCI interface:
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+ */
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+
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+#define DEBUG_CFG 0
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+
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+#if DEBUG_CFG
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+# define DBG_CFG(args) printk args
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+#else
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+# define DBG_CFG(args)
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+#endif
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+
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+/*
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+ * Given a bus, device, and function number, compute resulting
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+ * configuration space address and setup the MCPCIA_HAXR2 register
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+ * accordingly. It is therefore not safe to have concurrent
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+ * invocations to configuration space access routines, but there
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+ * really shouldn't be any need for this.
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+ *
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+ * Type 0:
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+ *
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+ * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
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+ * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
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+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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+ * | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0|
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+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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+ *
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+ * 31:11 Device select bit.
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+ * 10:8 Function number
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+ * 7:2 Register number
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+ *
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+ * Type 1:
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+ *
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+ * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
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+ * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
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+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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+ * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1|
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+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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+ *
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+ * 31:24 reserved
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+ * 23:16 bus number (8 bits = 128 possible buses)
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+ * 15:11 Device number (5 bits)
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+ * 10:8 function number
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+ * 7:2 register number
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+ *
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+ * Notes:
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+ * The function number selects which function of a multi-function device
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+ * (e.g., SCSI and Ethernet).
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+ *
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+ * The register selects a DWORD (32 bit) register offset. Hence it
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+ * doesn't get shifted by 2 bits as we want to "drop" the bottom two
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+ * bits.
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+ */
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+
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+static unsigned int
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+conf_read(unsigned long addr, unsigned char type1,
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+ struct pci_controller *hose)
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+{
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+ unsigned long flags;
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