|
@@ -774,3 +774,173 @@ static struct omap_hwmod am33xx_elm_hwmod = {
|
|
.class = &am33xx_elm_hwmod_class,
|
|
.class = &am33xx_elm_hwmod_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.mpu_irqs = am33xx_elm_irqs,
|
|
.mpu_irqs = am33xx_elm_irqs,
|
|
|
|
+ .main_clk = "l4ls_gclk",
|
|
|
|
+ .prcm = {
|
|
|
|
+ .omap4 = {
|
|
|
|
+ .clkctrl_offs = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
|
|
|
|
+ .modulemode = MODULEMODE_SWCTRL,
|
|
|
|
+ },
|
|
|
|
+ },
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+/*
|
|
|
|
+ * 'epwmss' class: ecap0,1,2, ehrpwm0,1,2
|
|
|
|
+ */
|
|
|
|
+static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
|
|
|
|
+ .rev_offs = 0x0,
|
|
|
|
+ .sysc_offs = 0x4,
|
|
|
|
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
|
|
|
|
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
|
|
+ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
|
|
|
|
+ MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
|
|
|
|
+ .sysc_fields = &omap_hwmod_sysc_type2,
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
|
|
|
|
+ .name = "epwmss",
|
|
|
|
+ .sysc = &am33xx_epwmss_sysc,
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+/* ehrpwm0 */
|
|
|
|
+static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
|
|
|
|
+ { .name = "int", .irq = 86 + OMAP_INTC_START, },
|
|
|
|
+ { .name = "tzint", .irq = 58 + OMAP_INTC_START, },
|
|
|
|
+ { .irq = -1 },
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
|
|
|
|
+ .name = "ehrpwm0",
|
|
|
|
+ .class = &am33xx_epwmss_hwmod_class,
|
|
|
|
+ .clkdm_name = "l4ls_clkdm",
|
|
|
|
+ .mpu_irqs = am33xx_ehrpwm0_irqs,
|
|
|
|
+ .main_clk = "l4ls_gclk",
|
|
|
|
+ .prcm = {
|
|
|
|
+ .omap4 = {
|
|
|
|
+ .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
|
|
|
|
+ .modulemode = MODULEMODE_SWCTRL,
|
|
|
|
+ },
|
|
|
|
+ },
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+/* ehrpwm1 */
|
|
|
|
+static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
|
|
|
|
+ { .name = "int", .irq = 87 + OMAP_INTC_START, },
|
|
|
|
+ { .name = "tzint", .irq = 59 + OMAP_INTC_START, },
|
|
|
|
+ { .irq = -1 },
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
|
|
|
|
+ .name = "ehrpwm1",
|
|
|
|
+ .class = &am33xx_epwmss_hwmod_class,
|
|
|
|
+ .clkdm_name = "l4ls_clkdm",
|
|
|
|
+ .mpu_irqs = am33xx_ehrpwm1_irqs,
|
|
|
|
+ .main_clk = "l4ls_gclk",
|
|
|
|
+ .prcm = {
|
|
|
|
+ .omap4 = {
|
|
|
|
+ .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
|
|
|
|
+ .modulemode = MODULEMODE_SWCTRL,
|
|
|
|
+ },
|
|
|
|
+ },
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+/* ehrpwm2 */
|
|
|
|
+static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
|
|
|
|
+ { .name = "int", .irq = 39 + OMAP_INTC_START, },
|
|
|
|
+ { .name = "tzint", .irq = 60 + OMAP_INTC_START, },
|
|
|
|
+ { .irq = -1 },
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
|
|
|
|
+ .name = "ehrpwm2",
|
|
|
|
+ .class = &am33xx_epwmss_hwmod_class,
|
|
|
|
+ .clkdm_name = "l4ls_clkdm",
|
|
|
|
+ .mpu_irqs = am33xx_ehrpwm2_irqs,
|
|
|
|
+ .main_clk = "l4ls_gclk",
|
|
|
|
+ .prcm = {
|
|
|
|
+ .omap4 = {
|
|
|
|
+ .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
|
|
|
|
+ .modulemode = MODULEMODE_SWCTRL,
|
|
|
|
+ },
|
|
|
|
+ },
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+/* ecap0 */
|
|
|
|
+static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
|
|
|
|
+ { .irq = 31 + OMAP_INTC_START, },
|
|
|
|
+ { .irq = -1 },
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+static struct omap_hwmod am33xx_ecap0_hwmod = {
|
|
|
|
+ .name = "ecap0",
|
|
|
|
+ .class = &am33xx_epwmss_hwmod_class,
|
|
|
|
+ .clkdm_name = "l4ls_clkdm",
|
|
|
|
+ .mpu_irqs = am33xx_ecap0_irqs,
|
|
|
|
+ .main_clk = "l4ls_gclk",
|
|
|
|
+ .prcm = {
|
|
|
|
+ .omap4 = {
|
|
|
|
+ .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
|
|
|
|
+ .modulemode = MODULEMODE_SWCTRL,
|
|
|
|
+ },
|
|
|
|
+ },
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+/* ecap1 */
|
|
|
|
+static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = {
|
|
|
|
+ { .irq = 47 + OMAP_INTC_START, },
|
|
|
|
+ { .irq = -1 },
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+static struct omap_hwmod am33xx_ecap1_hwmod = {
|
|
|
|
+ .name = "ecap1",
|
|
|
|
+ .class = &am33xx_epwmss_hwmod_class,
|
|
|
|
+ .clkdm_name = "l4ls_clkdm",
|
|
|
|
+ .mpu_irqs = am33xx_ecap1_irqs,
|
|
|
|
+ .main_clk = "l4ls_gclk",
|
|
|
|
+ .prcm = {
|
|
|
|
+ .omap4 = {
|
|
|
|
+ .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
|
|
|
|
+ .modulemode = MODULEMODE_SWCTRL,
|
|
|
|
+ },
|
|
|
|
+ },
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+/* ecap2 */
|
|
|
|
+static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = {
|
|
|
|
+ { .irq = 61 + OMAP_INTC_START, },
|
|
|
|
+ { .irq = -1 },
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+static struct omap_hwmod am33xx_ecap2_hwmod = {
|
|
|
|
+ .name = "ecap2",
|
|
|
|
+ .mpu_irqs = am33xx_ecap2_irqs,
|
|
|
|
+ .class = &am33xx_epwmss_hwmod_class,
|
|
|
|
+ .clkdm_name = "l4ls_clkdm",
|
|
|
|
+ .main_clk = "l4ls_gclk",
|
|
|
|
+ .prcm = {
|
|
|
|
+ .omap4 = {
|
|
|
|
+ .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
|
|
|
|
+ .modulemode = MODULEMODE_SWCTRL,
|
|
|
|
+ },
|
|
|
|
+ },
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+/*
|
|
|
|
+ * 'gpio' class: for gpio 0,1,2,3
|
|
|
|
+ */
|
|
|
|
+static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
|
|
|
|
+ .rev_offs = 0x0000,
|
|
|
|
+ .sysc_offs = 0x0010,
|
|
|
|
+ .syss_offs = 0x0114,
|
|
|
|
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
|
|
|
|
+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
|
|
|
|
+ SYSS_HAS_RESET_STATUS),
|
|
|
|
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
|
|
+ SIDLE_SMART_WKUP),
|
|
|
|
+ .sysc_fields = &omap_hwmod_sysc_type1,
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
|
|
|
|
+ .name = "gpio",
|
|
|
|
+ .sysc = &am33xx_gpio_sysc,
|
|
|
|
+ .rev = 2,
|
|
|
|
+};
|