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@@ -215,3 +215,148 @@ unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
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/* Calculate in picosecs to yield more exact results */
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tick_ps = gpmc_get_fclk_period();
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+ return (time_ps + tick_ps - 1) / tick_ps;
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+}
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+
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+unsigned int gpmc_ticks_to_ns(unsigned int ticks)
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+{
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+ return ticks * gpmc_get_fclk_period() / 1000;
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+}
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+
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+unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
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+{
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+ unsigned long ticks = gpmc_ns_to_ticks(time_ns);
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+
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+ return ticks * gpmc_get_fclk_period() / 1000;
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+}
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+
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+static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
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+{
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+ return ticks * gpmc_get_fclk_period();
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+}
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+
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+static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
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+{
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+ unsigned long ticks = gpmc_ps_to_ticks(time_ps);
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+
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+ return ticks * gpmc_get_fclk_period();
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+}
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+
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+static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
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+{
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+ u32 l;
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+
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+ l = gpmc_cs_read_reg(cs, reg);
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+ if (value)
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+ l |= mask;
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+ else
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+ l &= ~mask;
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+ gpmc_cs_write_reg(cs, reg, l);
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+}
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+
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+static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
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+{
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+ gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
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+ GPMC_CONFIG1_TIME_PARA_GRAN,
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+ p->time_para_granularity);
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+ gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
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+ GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
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+ gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
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+ GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
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+ gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
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+ GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
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+ gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
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+ GPMC_CONFIG4_OEEXTRADELAY, p->we_extra_delay);
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+ gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
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+ GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
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+ p->cycle2cyclesamecsen);
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+ gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
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+ GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
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+ p->cycle2cyclediffcsen);
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+}
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+
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+#ifdef DEBUG
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+static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
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+ int time, const char *name)
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+#else
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+static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
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+ int time)
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+#endif
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+{
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+ u32 l;
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+ int ticks, mask, nr_bits;
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+
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+ if (time == 0)
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+ ticks = 0;
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+ else
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+ ticks = gpmc_ns_to_ticks(time);
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+ nr_bits = end_bit - st_bit + 1;
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+ if (ticks >= 1 << nr_bits) {
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+#ifdef DEBUG
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+ printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
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+ cs, name, time, ticks, 1 << nr_bits);
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+#endif
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+ return -1;
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+ }
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+
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+ mask = (1 << nr_bits) - 1;
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+ l = gpmc_cs_read_reg(cs, reg);
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+#ifdef DEBUG
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+ printk(KERN_INFO
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+ "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
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+ cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
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+ (l >> st_bit) & mask, time);
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+#endif
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+ l &= ~(mask << st_bit);
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+ l |= ticks << st_bit;
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+ gpmc_cs_write_reg(cs, reg, l);
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+
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+ return 0;
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+}
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+
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+#ifdef DEBUG
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+#define GPMC_SET_ONE(reg, st, end, field) \
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+ if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
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+ t->field, #field) < 0) \
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+ return -1
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+#else
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+#define GPMC_SET_ONE(reg, st, end, field) \
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+ if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
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+ return -1
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+#endif
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+
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+int gpmc_calc_divider(unsigned int sync_clk)
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+{
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+ int div;
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+ u32 l;
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+
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+ l = sync_clk + (gpmc_get_fclk_period() - 1);
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+ div = l / gpmc_get_fclk_period();
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+ if (div > 4)
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+ return -1;
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+ if (div <= 0)
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+ div = 1;
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+
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+ return div;
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+}
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+
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+int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
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+{
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+ int div;
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+ u32 l;
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+
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+ div = gpmc_calc_divider(t->sync_clk);
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+ if (div < 0)
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+ return div;
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+
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+ GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
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+ GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
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+ GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
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+
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+ GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on);
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+ GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off);
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+ GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
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+
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+ GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on);
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+ GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off);
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+ GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
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