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@@ -60,3 +60,123 @@ void __init sh7372_map_io(void)
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iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc));
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iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc));
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}
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}
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+/* SCIFA0 */
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+static struct plat_sci_port scif0_platform_data = {
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+ .mapbase = 0xe6c40000,
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+ .flags = UPF_BOOT_AUTOCONF,
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+ .scscr = SCSCR_RE | SCSCR_TE,
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+ .scbrr_algo_id = SCBRR_ALGO_4,
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+ .type = PORT_SCIFA,
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+ .irqs = { evt2irq(0x0c00), evt2irq(0x0c00),
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+ evt2irq(0x0c00), evt2irq(0x0c00) },
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+};
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+
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+static struct platform_device scif0_device = {
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+ .name = "sh-sci",
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+ .id = 0,
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+ .dev = {
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+ .platform_data = &scif0_platform_data,
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+ },
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+};
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+
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+/* SCIFA1 */
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+static struct plat_sci_port scif1_platform_data = {
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+ .mapbase = 0xe6c50000,
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+ .flags = UPF_BOOT_AUTOCONF,
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+ .scscr = SCSCR_RE | SCSCR_TE,
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+ .scbrr_algo_id = SCBRR_ALGO_4,
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+ .type = PORT_SCIFA,
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+ .irqs = { evt2irq(0x0c20), evt2irq(0x0c20),
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+ evt2irq(0x0c20), evt2irq(0x0c20) },
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+};
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+
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+static struct platform_device scif1_device = {
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+ .name = "sh-sci",
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+ .id = 1,
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+ .dev = {
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+ .platform_data = &scif1_platform_data,
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+ },
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+};
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+
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+/* SCIFA2 */
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+static struct plat_sci_port scif2_platform_data = {
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+ .mapbase = 0xe6c60000,
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+ .flags = UPF_BOOT_AUTOCONF,
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+ .scscr = SCSCR_RE | SCSCR_TE,
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+ .scbrr_algo_id = SCBRR_ALGO_4,
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+ .type = PORT_SCIFA,
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+ .irqs = { evt2irq(0x0c40), evt2irq(0x0c40),
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+ evt2irq(0x0c40), evt2irq(0x0c40) },
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+};
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+
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+static struct platform_device scif2_device = {
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+ .name = "sh-sci",
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+ .id = 2,
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+ .dev = {
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+ .platform_data = &scif2_platform_data,
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+ },
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+};
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+
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+/* SCIFA3 */
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+static struct plat_sci_port scif3_platform_data = {
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+ .mapbase = 0xe6c70000,
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+ .flags = UPF_BOOT_AUTOCONF,
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+ .scscr = SCSCR_RE | SCSCR_TE,
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+ .scbrr_algo_id = SCBRR_ALGO_4,
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+ .type = PORT_SCIFA,
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+ .irqs = { evt2irq(0x0c60), evt2irq(0x0c60),
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+ evt2irq(0x0c60), evt2irq(0x0c60) },
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+};
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+
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+static struct platform_device scif3_device = {
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+ .name = "sh-sci",
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+ .id = 3,
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+ .dev = {
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+ .platform_data = &scif3_platform_data,
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+ },
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+};
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+
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+/* SCIFA4 */
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+static struct plat_sci_port scif4_platform_data = {
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+ .mapbase = 0xe6c80000,
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+ .flags = UPF_BOOT_AUTOCONF,
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+ .scscr = SCSCR_RE | SCSCR_TE,
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+ .scbrr_algo_id = SCBRR_ALGO_4,
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+ .type = PORT_SCIFA,
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+ .irqs = { evt2irq(0x0d20), evt2irq(0x0d20),
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+ evt2irq(0x0d20), evt2irq(0x0d20) },
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+};
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+
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+static struct platform_device scif4_device = {
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+ .name = "sh-sci",
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+ .id = 4,
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+ .dev = {
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+ .platform_data = &scif4_platform_data,
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+ },
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+};
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+
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+/* SCIFA5 */
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+static struct plat_sci_port scif5_platform_data = {
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+ .mapbase = 0xe6cb0000,
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+ .flags = UPF_BOOT_AUTOCONF,
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+ .scscr = SCSCR_RE | SCSCR_TE,
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+ .scbrr_algo_id = SCBRR_ALGO_4,
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+ .type = PORT_SCIFA,
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+ .irqs = { evt2irq(0x0d40), evt2irq(0x0d40),
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+ evt2irq(0x0d40), evt2irq(0x0d40) },
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+};
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+
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+static struct platform_device scif5_device = {
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+ .name = "sh-sci",
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+ .id = 5,
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+ .dev = {
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+ .platform_data = &scif5_platform_data,
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+ },
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+};
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+
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+/* SCIFB */
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+static struct plat_sci_port scif6_platform_data = {
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+ .mapbase = 0xe6c30000,
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+ .flags = UPF_BOOT_AUTOCONF,
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+ .scscr = SCSCR_RE | SCSCR_TE,
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+ .scbrr_algo_id = SCBRR_ALGO_4,
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