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@@ -1352,3 +1352,100 @@ static pinmux_enum_t pinmux_data[] = {
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PINMUX_DATA(TS_SPSYNC4_MARK, PORT265_FN3),
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PINMUX_DATA(SDHID2_1_MARK, PORT266_FN1), \
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PINMUX_DATA(TS_SDAT4_MARK, PORT266_FN3),
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+ PINMUX_DATA(SDHID2_2_MARK, PORT267_FN1), \
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+ PINMUX_DATA(TS_SDEN4_MARK, PORT267_FN3),
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+ PINMUX_DATA(SDHID2_3_MARK, PORT268_FN1), \
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+ PINMUX_DATA(TS_SCK4_MARK, PORT268_FN3),
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+ PINMUX_DATA(SDHICMD2_MARK, PORT269_FN1),
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+ PINMUX_DATA(MMCCLK0_MARK, PORT270_FN1, MSEL4CR_MSEL15_0),
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+ PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, PORT271_IN_PU,
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+ MSEL4CR_MSEL15_0),
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+ PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, PORT272_IN_PU,
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+ MSEL4CR_MSEL15_0),
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+ PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, PORT273_IN_PU,
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+ MSEL4CR_MSEL15_0),
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+ PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, PORT274_IN_PU,
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+ MSEL4CR_MSEL15_0),
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+ PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, PORT275_IN_PU,
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+ MSEL4CR_MSEL15_0), \
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+ PINMUX_DATA(TS_SPSYNC5_MARK, PORT275_FN3),
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+ PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, PORT276_IN_PU,
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+ MSEL4CR_MSEL15_0), \
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+ PINMUX_DATA(TS_SDAT5_MARK, PORT276_FN3),
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+ PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, PORT277_IN_PU,
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+ MSEL4CR_MSEL15_0), \
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+ PINMUX_DATA(TS_SDEN5_MARK, PORT277_FN3),
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+ PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, PORT278_IN_PU,
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+ MSEL4CR_MSEL15_0), \
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+ PINMUX_DATA(TS_SCK5_MARK, PORT278_FN3),
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+ PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, PORT279_IN_PU,
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+ MSEL4CR_MSEL15_0),
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+ PINMUX_DATA(RESETOUTS__MARK, PORT281_FN1), \
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+ PINMUX_DATA(EXTAL2OUT_MARK, PORT281_FN2),
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+ PINMUX_DATA(MCP_WAIT__MCP_FRB_MARK, PORT288_FN1),
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+ PINMUX_DATA(MCP_CKO_MARK, PORT289_FN1), \
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+ PINMUX_DATA(MMCCLK1_MARK, PORT289_FN2, MSEL4CR_MSEL15_1),
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+ PINMUX_DATA(MCP_D15_MCP_NAF15_MARK, PORT290_FN1),
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+ PINMUX_DATA(MCP_D14_MCP_NAF14_MARK, PORT291_FN1),
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+ PINMUX_DATA(MCP_D13_MCP_NAF13_MARK, PORT292_FN1),
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+ PINMUX_DATA(MCP_D12_MCP_NAF12_MARK, PORT293_FN1),
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+ PINMUX_DATA(MCP_D11_MCP_NAF11_MARK, PORT294_FN1),
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+ PINMUX_DATA(MCP_D10_MCP_NAF10_MARK, PORT295_FN1),
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+ PINMUX_DATA(MCP_D9_MCP_NAF9_MARK, PORT296_FN1),
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+ PINMUX_DATA(MCP_D8_MCP_NAF8_MARK, PORT297_FN1), \
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+ PINMUX_DATA(MMCCMD1_MARK, PORT297_FN2, MSEL4CR_MSEL15_1),
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+ PINMUX_DATA(MCP_D7_MCP_NAF7_MARK, PORT298_FN1), \
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+ PINMUX_DATA(MMCD1_7_MARK, PORT298_FN2, MSEL4CR_MSEL15_1),
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+
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+ PINMUX_DATA(MCP_D6_MCP_NAF6_MARK, PORT299_FN1), \
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+ PINMUX_DATA(MMCD1_6_MARK, PORT299_FN2, MSEL4CR_MSEL15_1),
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+ PINMUX_DATA(MCP_D5_MCP_NAF5_MARK, PORT300_FN1), \
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+ PINMUX_DATA(MMCD1_5_MARK, PORT300_FN2, MSEL4CR_MSEL15_1),
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+ PINMUX_DATA(MCP_D4_MCP_NAF4_MARK, PORT301_FN1), \
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+ PINMUX_DATA(MMCD1_4_MARK, PORT301_FN2, MSEL4CR_MSEL15_1),
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+ PINMUX_DATA(MCP_D3_MCP_NAF3_MARK, PORT302_FN1), \
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+ PINMUX_DATA(MMCD1_3_MARK, PORT302_FN2, MSEL4CR_MSEL15_1),
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+ PINMUX_DATA(MCP_D2_MCP_NAF2_MARK, PORT303_FN1), \
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+ PINMUX_DATA(MMCD1_2_MARK, PORT303_FN2, MSEL4CR_MSEL15_1),
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+ PINMUX_DATA(MCP_D1_MCP_NAF1_MARK, PORT304_FN1), \
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+ PINMUX_DATA(MMCD1_1_MARK, PORT304_FN2, MSEL4CR_MSEL15_1),
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+ PINMUX_DATA(MCP_D0_MCP_NAF0_MARK, PORT305_FN1), \
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+ PINMUX_DATA(MMCD1_0_MARK, PORT305_FN2, MSEL4CR_MSEL15_1),
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+ PINMUX_DATA(MCP_NBRSTOUT__MARK, PORT306_FN1),
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+ PINMUX_DATA(MCP_WE0__MCP_FWE_MARK, PORT309_FN1), \
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+ PINMUX_DATA(MCP_RDWR_MCP_FWE_MARK, PORT309_FN2),
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+
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+ /* MSEL2 special cases */
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+ PINMUX_DATA(TSIF2_TS_XX1_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
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+ MSEL2CR_MSEL12_0),
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+ PINMUX_DATA(TSIF2_TS_XX2_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
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+ MSEL2CR_MSEL12_1),
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+ PINMUX_DATA(TSIF2_TS_XX3_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
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+ MSEL2CR_MSEL12_0),
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+ PINMUX_DATA(TSIF2_TS_XX4_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
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+ MSEL2CR_MSEL12_1),
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+ PINMUX_DATA(TSIF2_TS_XX5_MARK, MSEL2CR_MSEL14_1, MSEL2CR_MSEL13_0,
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+ MSEL2CR_MSEL12_0),
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+ PINMUX_DATA(TSIF1_TS_XX1_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
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+ MSEL2CR_MSEL9_0),
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+ PINMUX_DATA(TSIF1_TS_XX2_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
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+ MSEL2CR_MSEL9_1),
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+ PINMUX_DATA(TSIF1_TS_XX3_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
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+ MSEL2CR_MSEL9_0),
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+ PINMUX_DATA(TSIF1_TS_XX4_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
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+ MSEL2CR_MSEL9_1),
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+ PINMUX_DATA(TSIF1_TS_XX5_MARK, MSEL2CR_MSEL11_1, MSEL2CR_MSEL10_0,
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+ MSEL2CR_MSEL9_0),
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+ PINMUX_DATA(TSIF0_TS_XX1_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
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+ MSEL2CR_MSEL6_0),
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+ PINMUX_DATA(TSIF0_TS_XX2_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
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+ MSEL2CR_MSEL6_1),
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+ PINMUX_DATA(TSIF0_TS_XX3_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
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+ MSEL2CR_MSEL6_0),
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+ PINMUX_DATA(TSIF0_TS_XX4_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
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+ MSEL2CR_MSEL6_1),
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+ PINMUX_DATA(TSIF0_TS_XX5_MARK, MSEL2CR_MSEL8_1, MSEL2CR_MSEL7_0,
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+ MSEL2CR_MSEL6_0),
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+ PINMUX_DATA(MST1_TS_XX1_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
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+ MSEL2CR_MSEL3_0),
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+ PINMUX_DATA(MST1_TS_XX2_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
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