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@@ -187,3 +187,160 @@
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#define MX51_DMA_REQ_ATA_TX_END 4
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#define MX51_DMA_REQ_SLIM_B 5
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#define MX51_DMA_REQ_CSPI1_RX 6
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+#define MX51_DMA_REQ_CSPI1_TX 7
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+#define MX51_DMA_REQ_CSPI2_RX 8
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+#define MX51_DMA_REQ_CSPI2_TX 9
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+#define MX51_DMA_REQ_HS_I2C_TX 10
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+#define MX51_DMA_REQ_HS_I2C_RX 11
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+#define MX51_DMA_REQ_FIRI_RX 12
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+#define MX51_DMA_REQ_FIRI_TX 13
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+#define MX51_DMA_REQ_EXTREQ1 14
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+#define MX51_DMA_REQ_GPU 15
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+#define MX51_DMA_REQ_UART2_RX 16
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+#define MX51_DMA_REQ_UART2_TX 17
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+#define MX51_DMA_REQ_UART1_RX 18
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+#define MX51_DMA_REQ_UART1_TX 19
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+#define MX51_DMA_REQ_SDHC1 20
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+#define MX51_DMA_REQ_SDHC2 21
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+#define MX51_DMA_REQ_SSI2_RX1 22
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+#define MX51_DMA_REQ_SSI2_TX1 23
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+#define MX51_DMA_REQ_SSI2_RX0 24
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+#define MX51_DMA_REQ_SSI2_TX0 25
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+#define MX51_DMA_REQ_SSI1_RX1 26
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+#define MX51_DMA_REQ_SSI1_TX1 27
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+#define MX51_DMA_REQ_SSI1_RX0 28
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+#define MX51_DMA_REQ_SSI1_TX0 29
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+#define MX51_DMA_REQ_EMI_RD 30
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+#define MX51_DMA_REQ_CTI2_0 31
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+#define MX51_DMA_REQ_EMI_WR 32
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+#define MX51_DMA_REQ_CTI2_1 33
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+#define MX51_DMA_REQ_EPIT2 34
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+#define MX51_DMA_REQ_SSI3_RX1 35
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+#define MX51_DMA_REQ_IPU 36
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+#define MX51_DMA_REQ_SSI3_TX1 37
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+#define MX51_DMA_REQ_CSPI_RX 38
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+#define MX51_DMA_REQ_CSPI_TX 39
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+#define MX51_DMA_REQ_SDHC3 40
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+#define MX51_DMA_REQ_SDHC4 41
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+#define MX51_DMA_REQ_SLIM_B_TX 42
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+#define MX51_DMA_REQ_UART3_RX 43
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+#define MX51_DMA_REQ_UART3_TX 44
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+#define MX51_DMA_REQ_SPDIF 45
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+#define MX51_DMA_REQ_SSI3_RX0 46
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+#define MX51_DMA_REQ_SSI3_TX0 47
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+
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+/*
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+ * Interrupt numbers
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+ */
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+#include <asm/irq.h>
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+#define MX51_INT_BASE (NR_IRQS_LEGACY + 0)
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+#define MX51_INT_RESV0 (NR_IRQS_LEGACY + 0)
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+#define MX51_INT_ESDHC1 (NR_IRQS_LEGACY + 1)
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+#define MX51_INT_ESDHC2 (NR_IRQS_LEGACY + 2)
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+#define MX51_INT_ESDHC3 (NR_IRQS_LEGACY + 3)
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+#define MX51_INT_ESDHC4 (NR_IRQS_LEGACY + 4)
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+#define MX51_INT_RESV5 (NR_IRQS_LEGACY + 5)
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+#define MX51_INT_SDMA (NR_IRQS_LEGACY + 6)
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+#define MX51_INT_IOMUX (NR_IRQS_LEGACY + 7)
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+#define MX51_INT_NFC (NR_IRQS_LEGACY + 8)
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+#define MX51_INT_VPU (NR_IRQS_LEGACY + 9)
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+#define MX51_INT_IPU_ERR (NR_IRQS_LEGACY + 10)
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+#define MX51_INT_IPU_SYN (NR_IRQS_LEGACY + 11)
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+#define MX51_INT_GPU (NR_IRQS_LEGACY + 12)
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+#define MX51_INT_RESV13 (NR_IRQS_LEGACY + 13)
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+#define MX51_INT_USB_HS1 (NR_IRQS_LEGACY + 14)
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+#define MX51_INT_EMI (NR_IRQS_LEGACY + 15)
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+#define MX51_INT_USB_HS2 (NR_IRQS_LEGACY + 16)
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+#define MX51_INT_USB_HS3 (NR_IRQS_LEGACY + 17)
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+#define MX51_INT_USB_OTG (NR_IRQS_LEGACY + 18)
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+#define MX51_INT_SAHARA_H0 (NR_IRQS_LEGACY + 19)
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+#define MX51_INT_SAHARA_H1 (NR_IRQS_LEGACY + 20)
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+#define MX51_INT_SCC_SMN (NR_IRQS_LEGACY + 21)
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+#define MX51_INT_SCC_STZ (NR_IRQS_LEGACY + 22)
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+#define MX51_INT_SCC_SCM (NR_IRQS_LEGACY + 23)
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+#define MX51_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24)
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+#define MX51_INT_SRTC_TZ (NR_IRQS_LEGACY + 25)
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+#define MX51_INT_RTIC (NR_IRQS_LEGACY + 26)
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+#define MX51_INT_CSU (NR_IRQS_LEGACY + 27)
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+#define MX51_INT_SLIM_B (NR_IRQS_LEGACY + 28)
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+#define MX51_INT_SSI1 (NR_IRQS_LEGACY + 29)
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+#define MX51_INT_SSI2 (NR_IRQS_LEGACY + 30)
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+#define MX51_INT_UART1 (NR_IRQS_LEGACY + 31)
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+#define MX51_INT_UART2 (NR_IRQS_LEGACY + 32)
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+#define MX51_INT_UART3 (NR_IRQS_LEGACY + 33)
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+#define MX51_INT_RESV34 (NR_IRQS_LEGACY + 34)
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+#define MX51_INT_RESV35 (NR_IRQS_LEGACY + 35)
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+#define MX51_INT_ECSPI1 (NR_IRQS_LEGACY + 36)
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+#define MX51_INT_ECSPI2 (NR_IRQS_LEGACY + 37)
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+#define MX51_INT_CSPI (NR_IRQS_LEGACY + 38)
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+#define MX51_INT_GPT (NR_IRQS_LEGACY + 39)
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+#define MX51_INT_EPIT1 (NR_IRQS_LEGACY + 40)
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+#define MX51_INT_EPIT2 (NR_IRQS_LEGACY + 41)
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+#define MX51_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42)
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+#define MX51_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43)
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+#define MX51_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44)
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+#define MX51_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45)
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+#define MX51_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46)
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+#define MX51_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47)
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+#define MX51_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48)
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+#define MX51_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49)
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+#define MX51_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50)
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+#define MX51_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51)
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+#define MX51_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52)
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+#define MX51_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53)
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+#define MX51_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54)
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+#define MX51_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55)
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+#define MX51_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56)
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+#define MX51_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57)
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+#define MX51_INT_WDOG1 (NR_IRQS_LEGACY + 58)
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+#define MX51_INT_WDOG2 (NR_IRQS_LEGACY + 59)
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+#define MX51_INT_KPP (NR_IRQS_LEGACY + 60)
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+#define MX51_INT_PWM1 (NR_IRQS_LEGACY + 61)
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+#define MX51_INT_I2C1 (NR_IRQS_LEGACY + 62)
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+#define MX51_INT_I2C2 (NR_IRQS_LEGACY + 63)
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+#define MX51_INT_HS_I2C (NR_IRQS_LEGACY + 64)
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+#define MX51_INT_RESV65 (NR_IRQS_LEGACY + 65)
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+#define MX51_INT_RESV66 (NR_IRQS_LEGACY + 66)
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+#define MX51_INT_SIM_IPB (NR_IRQS_LEGACY + 67)
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+#define MX51_INT_SIM_DAT (NR_IRQS_LEGACY + 68)
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+#define MX51_INT_IIM (NR_IRQS_LEGACY + 69)
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+#define MX51_INT_ATA (NR_IRQS_LEGACY + 70)
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+#define MX51_INT_CCM1 (NR_IRQS_LEGACY + 71)
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+#define MX51_INT_CCM2 (NR_IRQS_LEGACY + 72)
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+#define MX51_INT_GPC1 (NR_IRQS_LEGACY + 73)
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+#define MX51_INT_GPC2 (NR_IRQS_LEGACY + 74)
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+#define MX51_INT_SRC (NR_IRQS_LEGACY + 75)
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+#define MX51_INT_NM (NR_IRQS_LEGACY + 76)
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+#define MX51_INT_PMU (NR_IRQS_LEGACY + 77)
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+#define MX51_INT_CTI_IRQ (NR_IRQS_LEGACY + 78)
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+#define MX51_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79)
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+#define MX51_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80)
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+#define MX51_INT_MCG_ERR (NR_IRQS_LEGACY + 81)
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+#define MX51_INT_MCG_TMR (NR_IRQS_LEGACY + 82)
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+#define MX51_INT_MCG_FUNC (NR_IRQS_LEGACY + 83)
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+#define MX51_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84)
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+#define MX51_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85)
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+#define MX51_INT_RESV86 (NR_IRQS_LEGACY + 86)
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+#define MX51_INT_FEC (NR_IRQS_LEGACY + 87)
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+#define MX51_INT_OWIRE (NR_IRQS_LEGACY + 88)
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+#define MX51_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89)
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+#define MX51_INT_SJC (NR_IRQS_LEGACY + 90)
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+#define MX51_INT_SPDIF (NR_IRQS_LEGACY + 91)
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+#define MX51_INT_TVE (NR_IRQS_LEGACY + 92)
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+#define MX51_INT_FIRI (NR_IRQS_LEGACY + 93)
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+#define MX51_INT_PWM2 (NR_IRQS_LEGACY + 94)
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+#define MX51_INT_SLIM_EXP (NR_IRQS_LEGACY + 95)
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+#define MX51_INT_SSI3 (NR_IRQS_LEGACY + 96)
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+#define MX51_INT_EMI_BOOT (NR_IRQS_LEGACY + 97)
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+#define MX51_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98)
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+#define MX51_INT_SMC_RX (NR_IRQS_LEGACY + 99)
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+#define MX51_INT_VPU_IDLE (NR_IRQS_LEGACY + 100)
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+#define MX51_INT_EMI_NFC (NR_IRQS_LEGACY + 101)
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+#define MX51_INT_GPU_IDLE (NR_IRQS_LEGACY + 102)
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+
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+#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
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+extern int mx51_revision(void);
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+extern void mx51_display_revision(void);
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+#endif
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+
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+#endif /* ifndef __MACH_MX51_H__ */
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