|
@@ -197,3 +197,19 @@ typedef struct pal_cache_config_info_s {
|
|
|
#define pcci_stride pcci_info_1.pcci1_bits.stride
|
|
|
#define pcci_line_size pcci_info_1.pcci1_bits.line_size
|
|
|
#define pcci_assoc pcci_info_1.pcci1_bits.associativity
|
|
|
+#define pcci_cache_attr pcci_info_1.pcci1_bits.at
|
|
|
+#define pcci_unified pcci_info_1.pcci1_bits.u
|
|
|
+#define pcci_tag_msb pcci_info_2.pcci2_bits.tag_ms_bit
|
|
|
+#define pcci_tag_lsb pcci_info_2.pcci2_bits.tag_ls_bit
|
|
|
+#define pcci_alias_boundary pcci_info_2.pcci2_bits.alias_boundary
|
|
|
+#define pcci_cache_size pcci_info_2.pcci2_bits.cache_size
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+/* Possible values for cache attributes */
|
|
|
+
|
|
|
+#define PAL_CACHE_ATTR_WT 0 /* Write through cache */
|
|
|
+#define PAL_CACHE_ATTR_WB 1 /* Write back cache */
|
|
|
+#define PAL_CACHE_ATTR_WT_OR_WB 2 /* Either write thru or write
|
|
|
+ * back depending on TLB
|
|
|
+ * memory attributes
|