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@@ -183,3 +183,101 @@ static void omap2_enter_mpu_retention(void)
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/* REVISIT: These write to reserved bits? */
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omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
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omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
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+ omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
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+
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+ /* Try to enter MPU retention */
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+ omap2_prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
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+ OMAP_LOGICRETSTATE_MASK,
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+ MPU_MOD, OMAP2_PM_PWSTCTRL);
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+ } else {
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+ /* Block MPU retention */
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+
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+ omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
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+ OMAP2_PM_PWSTCTRL);
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+ }
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+
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+ omap2_sram_idle();
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+}
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+
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+static int omap2_can_sleep(void)
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+{
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+ if (omap2_fclks_active())
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+ return 0;
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+ if (__clk_is_enabled(osc_ck))
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+ return 0;
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+ if (omap_dma_running())
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+ return 0;
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+
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+ return 1;
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+}
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+
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+static void omap2_pm_idle(void)
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+{
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+ local_fiq_disable();
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+
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+ if (!omap2_can_sleep()) {
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+ if (omap_irq_pending())
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+ goto out;
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+ omap2_enter_mpu_retention();
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+ goto out;
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+ }
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+
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+ if (omap_irq_pending())
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+ goto out;
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+
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+ omap2_enter_full_retention();
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+
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+out:
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+ local_fiq_enable();
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+}
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+
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+static void __init prcm_setup_regs(void)
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+{
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+ int i, num_mem_banks;
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+ struct powerdomain *pwrdm;
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+
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+ /*
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+ * Enable autoidle
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+ * XXX This should be handled by hwmod code or PRCM init code
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+ */
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+ omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
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+ OMAP2_PRCM_SYSCONFIG_OFFSET);
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+
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+ /*
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+ * Set CORE powerdomain memory banks to retain their contents
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+ * during RETENTION
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+ */
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+ num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
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+ for (i = 0; i < num_mem_banks; i++)
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+ pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
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+
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+ /* Set CORE powerdomain's next power state to RETENTION */
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+ pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
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+
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+ /*
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+ * Set MPU powerdomain's next power state to RETENTION;
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+ * preserve logic state during retention
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+ */
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+ pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
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+ pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
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+
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+ /* Force-power down DSP, GFX powerdomains */
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+
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+ pwrdm = clkdm_get_pwrdm(dsp_clkdm);
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+ pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
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+ clkdm_sleep(dsp_clkdm);
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+
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+ pwrdm = clkdm_get_pwrdm(gfx_clkdm);
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+ pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
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+ clkdm_sleep(gfx_clkdm);
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+
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+ /* Enable hardware-supervised idle for all clkdms */
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+ clkdm_for_each(omap_pm_clkdms_setup, NULL);
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+ clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
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+
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+#ifdef CONFIG_SUSPEND
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+ omap_pm_suspend = omap2_enter_full_retention;
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+#endif
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+
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+ /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
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+ * stabilisation */
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