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@@ -1158,3 +1158,64 @@ static const struct clksel emu_src_clksel[] = {
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{ .parent = &sys_ck, .rates = emu_src_sys_rates },
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{ .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
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{ .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates },
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+ { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates },
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+ { .parent = NULL },
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+};
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+
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+static const struct clk_ops emu_src_ck_ops = {
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+ .init = &omap2_init_clk_clkdm,
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+ .recalc_rate = &omap2_clksel_recalc,
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+ .get_parent = &omap2_clksel_find_parent_index,
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+ .set_parent = &omap2_clksel_set_parent,
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+ .enable = &omap2_clkops_enable_clkdm,
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+ .disable = &omap2_clkops_disable_clkdm,
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+};
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+
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+static struct clk emu_src_ck;
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+
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+static struct clk_hw_omap emu_src_ck_hw = {
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+ .hw = {
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+ .clk = &emu_src_ck,
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+ },
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+ .clksel = emu_src_clksel,
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+ .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
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+ .clksel_mask = OMAP3430_MUX_CTRL_MASK,
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+ .clkdm_name = "emu_clkdm",
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+};
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+
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+DEFINE_STRUCT_CLK(emu_src_ck, emu_src_ck_parent_names, emu_src_ck_ops);
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+
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+DEFINE_CLK_DIVIDER(atclk_fck, "emu_src_ck", &emu_src_ck, 0x0,
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+ OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
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+ OMAP3430_CLKSEL_ATCLK_SHIFT, OMAP3430_CLKSEL_ATCLK_WIDTH,
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+ CLK_DIVIDER_ONE_BASED, NULL);
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+
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+static struct clk fac_ick;
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+
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+static struct clk_hw_omap fac_ick_hw = {
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+ .hw = {
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+ .clk = &fac_ick,
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+ },
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+ .ops = &clkhwops_iclk_wait,
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+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
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+ .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
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+ .clkdm_name = "core_l4_clkdm",
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+};
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+
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+DEFINE_STRUCT_CLK(fac_ick, aes2_ick_parent_names, aes2_ick_ops);
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+
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+static struct clk fshostusb_fck;
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+
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+static const char *fshostusb_fck_parent_names[] = {
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+ "core_48m_fck",
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+};
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+
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+static struct clk_hw_omap fshostusb_fck_hw = {
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+ .hw = {
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+ .clk = &fshostusb_fck,
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+ },
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+ .ops = &clkhwops_wait,
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+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
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+ .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
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+ .clkdm_name = "core_l4_clkdm",
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+};
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