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@@ -1110,3 +1110,91 @@
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#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */
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#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */
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#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */
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+#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */
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+#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */
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+#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */
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+#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */
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+#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */
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+#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */
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+#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */
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+#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */
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+#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */
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+#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */
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+#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */
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+#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */
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+#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */
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+#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */
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+#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */
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+#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */
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+#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */
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+#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */
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+#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */
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+#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */
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+#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */
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+#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */
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+#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */
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+#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */
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+#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */
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+#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */
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+#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */
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+#define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */
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+#define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */
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+#define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */
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+#define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */
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+#define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */
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+#define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */
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+#define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */
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+#define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */
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+#define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */
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+
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+#define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */
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+#define B1RDYPOL 0x00020000 /* B1 RDY Active High */
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+#define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */
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+#define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */
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+#define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */
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+#define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */
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+#define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */
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+#define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */
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+#define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */
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+#define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */
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+#define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */
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+#define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */
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+#define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */
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+#define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */
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+#define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */
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+#define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */
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+#define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */
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+#define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */
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+#define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */
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+#define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */
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+#define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */
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+#define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */
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+#define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */
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+#define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */
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+#define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */
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+#define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */
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+#define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */
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+#define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */
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+#define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */
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+#define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */
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+#define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */
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+#define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */
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+#define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */
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+#define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */
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+#define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */
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+#define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */
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+#define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */
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+#define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */
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+#define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */
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+#define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */
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+#define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */
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+#define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */
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+#define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */
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+#define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */
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+
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+/* EBIU_AMBCTL1 Masks */
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+#define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */
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+#define B2RDYPOL 0x00000002 /* B2 RDY Active High */
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+#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */
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+#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */
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+#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */
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