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@@ -157,3 +157,102 @@
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#define SPI_IMSK_SET_RSM 0x00000100 /* Receive Start Interrupt Mask */
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#define SPI_IMSK_SET_TSM 0x00000200 /* Transmit Start Interrupt Mask */
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#define SPI_IMSK_SET_RFM 0x00000400 /* Receive Finish Interrupt Mask */
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+#define SPI_IMSK_SET_TFM 0x00000800 /* Transmit Finish Interrupt Mask */
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+/* SPI_STATUS */
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+#define SPI_STAT_SPIF 0x00000001 /* SPI Finished */
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+#define SPI_STAT_RUWM 0x00000002 /* Receive Urgent Water-Mark Breached */
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+#define SPI_STAT_TUWM 0x00000004 /* Transmit Urgent Water-Mark Breached */
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+#define SPI_STAT_ROE 0x00000010 /* Receive Over-Run Error Indication */
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+#define SPI_STAT_TUE 0x00000020 /* Transmit Under-Run Error Indication */
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+#define SPI_STAT_TCE 0x00000040 /* Transmit Collision Error Indication */
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+#define SPI_STAT_MODF 0x00000080 /* Mode Fault Error Indication */
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+#define SPI_STAT_RS 0x00000100 /* Receive Start Indication */
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+#define SPI_STAT_TS 0x00000200 /* Transmit Start Indication */
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+#define SPI_STAT_RF 0x00000400 /* Receive Finish Indication */
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+#define SPI_STAT_TF 0x00000800 /* Transmit Finish Indication */
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+#define SPI_STAT_RFS 0x00007000 /* SPI_RFIFO status */
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+#define SPI_STAT_RFIFO_EMPTY 0x00000000 /* RFS: RFIFO Empty */
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+#define SPI_STAT_RFIFO_25 0x00001000 /* RFS: RFIFO 25% Full */
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+#define SPI_STAT_RFIFO_50 0x00002000 /* RFS: RFIFO 50% Full */
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+#define SPI_STAT_RFIFO_75 0x00003000 /* RFS: RFIFO 75% Full */
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+#define SPI_STAT_RFIFO_FULL 0x00004000 /* RFS: RFIFO Full */
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+#define SPI_STAT_TFS 0x00070000 /* SPI_TFIFO status */
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+#define SPI_STAT_TFIFO_FULL 0x00000000 /* TFS: TFIFO full */
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+#define SPI_STAT_TFIFO_25 0x00010000 /* TFS: TFIFO 25% empty */
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+#define SPI_STAT_TFIFO_50 0x00020000 /* TFS: TFIFO 50% empty */
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+#define SPI_STAT_TFIFO_75 0x00030000 /* TFS: TFIFO 75% empty */
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+#define SPI_STAT_TFIFO_EMPTY 0x00040000 /* TFS: TFIFO empty */
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+#define SPI_STAT_FCS 0x00100000 /* Flow-Control Stall Indication */
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+#define SPI_STAT_RFE 0x00400000 /* SPI_RFIFO Empty */
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+#define SPI_STAT_TFF 0x00800000 /* SPI_TFIFO Full */
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+/* SPI_ILAT */
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+#define SPI_ILAT_RUWMI 0x00000002 /* Receive Urgent Water Mark Interrupt */
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+#define SPI_ILAT_TUWMI 0x00000004 /* Transmit Urgent Water Mark Interrupt */
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+#define SPI_ILAT_ROI 0x00000010 /* Receive Over-Run Error Indication */
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+#define SPI_ILAT_TUI 0x00000020 /* Transmit Under-Run Error Indication */
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+#define SPI_ILAT_TCI 0x00000040 /* Transmit Collision Error Indication */
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+#define SPI_ILAT_MFI 0x00000080 /* Mode Fault Error Indication */
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+#define SPI_ILAT_RSI 0x00000100 /* Receive Start Indication */
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+#define SPI_ILAT_TSI 0x00000200 /* Transmit Start Indication */
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+#define SPI_ILAT_RFI 0x00000400 /* Receive Finish Indication */
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+#define SPI_ILAT_TFI 0x00000800 /* Transmit Finish Indication */
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+/* SPI_ILATCL */
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+#define SPI_ILAT_CLR_RUWMI 0x00000002 /* Receive Urgent Water Mark Interrupt */
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+#define SPI_ILAT_CLR_TUWMI 0x00000004 /* Transmit Urgent Water Mark Interrupt */
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+#define SPI_ILAT_CLR_ROI 0x00000010 /* Receive Over-Run Error Indication */
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+#define SPI_ILAT_CLR_TUI 0x00000020 /* Transmit Under-Run Error Indication */
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+#define SPI_ILAT_CLR_TCI 0x00000040 /* Transmit Collision Error Indication */
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+#define SPI_ILAT_CLR_MFI 0x00000080 /* Mode Fault Error Indication */
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+#define SPI_ILAT_CLR_RSI 0x00000100 /* Receive Start Indication */
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+#define SPI_ILAT_CLR_TSI 0x00000200 /* Transmit Start Indication */
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+#define SPI_ILAT_CLR_RFI 0x00000400 /* Receive Finish Indication */
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+#define SPI_ILAT_CLR_TFI 0x00000800 /* Transmit Finish Indication */
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+
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+/*
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+ * bfin spi3 registers layout
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+ */
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+struct bfin_spi_regs {
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+ u32 revid;
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+ u32 control;
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+ u32 rx_control;
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+ u32 tx_control;
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+ u32 clock;
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+ u32 delay;
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+ u32 ssel;
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+ u32 rwc;
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+ u32 rwcr;
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+ u32 twc;
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+ u32 twcr;
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+ u32 reserved0;
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+ u32 emask;
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+ u32 emaskcl;
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+ u32 emaskst;
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+ u32 reserved1;
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+ u32 status;
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+ u32 elat;
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+ u32 elatcl;
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+ u32 reserved2;
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+ u32 rfifo;
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+ u32 reserved3;
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+ u32 tfifo;
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+};
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+
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+#define MAX_CTRL_CS 8 /* cs in spi controller */
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+
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+/* device.platform_data for SSP controller devices */
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+struct bfin6xx_spi_master {
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+ u16 num_chipselect;
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+ u16 pin_req[7];
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+};
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+
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+/* spi_board_info.controller_data for SPI slave devices,
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+ * copied to spi_device.platform_data ... mostly for dma tuning
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+ */
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+struct bfin6xx_spi_chip {
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+ u32 control;
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+ u16 cs_chg_udelay; /* Some devices require 16-bit delays */
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+ u32 tx_dummy_val; /* tx value for rx only transfer */
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+ bool enable_dma;
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+};
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+
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+#endif /* _SPI_CHANNEL_H_ */
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