| 
					
				 | 
			
			
				@@ -1151,3 +1151,39 @@ 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				  
			 | 
		
	
		
			
				 | 
				 | 
			
			
				 /* Register read/write macros */ 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				 #define MCF_SDRAMC_SDMR			0xFC0B8000 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define MCF_SDRAMC_SDCR			0xFC0B8004 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define MCF_SDRAMC_SDCFG1		0xFC0B8008 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define MCF_SDRAMC_SDCFG2		0xFC0B800C 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define MCF_SDRAMC_LIMP_FIX		0xFC0B8080 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define MCF_SDRAMC_SDDS			0xFC0B8100 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define MCF_SDRAMC_SDCS0		0xFC0B8110 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define MCF_SDRAMC_SDCS1		0xFC0B8114 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define MCF_SDRAMC_SDCS2		0xFC0B8118 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define MCF_SDRAMC_SDCS3		0xFC0B811C 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+ 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+/* Bit definitions and macros for MCF_SDRAMC_SDMR */ 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define MCF_SDRAMC_SDMR_CMD		(0x00010000) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define MCF_SDRAMC_SDMR_AD(x)		(((x)&0x00000FFF)<<18) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define MCF_SDRAMC_SDMR_BNKAD(x)	(((x)&0x00000003)<<30) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define MCF_SDRAMC_SDMR_BNKAD_LMR	(0x00000000) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define MCF_SDRAMC_SDMR_BNKAD_LEMR	(0x40000000) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+ 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+/* Bit definitions and macros for MCF_SDRAMC_SDCR */ 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define MCF_SDRAMC_SDCR_IPALL		(0x00000002) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define MCF_SDRAMC_SDCR_IREF		(0x00000004) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define MCF_SDRAMC_SDCR_DQS_OE(x)	(((x)&0x0000000F)<<8) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define MCF_SDRAMC_SDCR_PS(x)		(((x)&0x00000003)<<12) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define MCF_SDRAMC_SDCR_RCNT(x)		(((x)&0x0000003F)<<16) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define MCF_SDRAMC_SDCR_OE_RULE		(0x00400000) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define MCF_SDRAMC_SDCR_MUX(x)		(((x)&0x00000003)<<24) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define MCF_SDRAMC_SDCR_REF		(0x10000000) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define MCF_SDRAMC_SDCR_DDR		(0x20000000) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define MCF_SDRAMC_SDCR_CKE		(0x40000000) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define MCF_SDRAMC_SDCR_MODE_EN		(0x80000000) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define MCF_SDRAMC_SDCR_PS_16		(0x00002000) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define MCF_SDRAMC_SDCR_PS_32		(0x00000000) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+ 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */ 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define MCF_SDRAMC_SDCFG1_WTLAT(x)	(((x)&0x00000007)<<4) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define MCF_SDRAMC_SDCFG1_REF2ACT(x)	(((x)&0x0000000F)<<8) 
			 | 
		
	
		
			
				 | 
				 | 
			
			
				+#define MCF_SDRAMC_SDCFG1_PRE2ACT(x)	(((x)&0x00000007)<<12) 
			 |