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@@ -270,3 +270,167 @@
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#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
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#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0,val)
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#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
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+#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1,val)
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+#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
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+#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2,val)
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+#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
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+#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3,val)
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+
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+/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
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+#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
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+#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1,val)
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+#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
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+#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2,val)
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+#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
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+#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV,val)
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+#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
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+#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV,val)
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+#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
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+#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX,val)
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+#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
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+#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX,val)
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+#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX)
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+#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX,val)
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+#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX)
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+#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX,val)
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+#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX)
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+#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX,val)
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+#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX)
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+#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX,val)
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+#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
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+#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1,val)
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+#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
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+#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2,val)
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+#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
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+#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV,val)
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+#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
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+#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV,val)
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+#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
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+#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT,val)
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+#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
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+#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL,val)
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+#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
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+#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1,val)
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+#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
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+#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2,val)
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+#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
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+#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0,val)
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+#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
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+#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1,val)
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+#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
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+#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2,val)
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+#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
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+#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3,val)
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+#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
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+#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0,val)
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+#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
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+#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1,val)
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+#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
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+#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2,val)
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+#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
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+#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3,val)
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+
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+/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
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+#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
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+#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL,val)
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+#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
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+#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val)
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+#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
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+#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val)
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+#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
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+#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL,val)
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+#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
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+#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL,val)
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+#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
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+#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val)
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+#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
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+#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val)
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+
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+/* DMA Traffic Control Registers */
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+#define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER)
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+#define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER,val)
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+#define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT)
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+#define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT,val)
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+
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+/* DMA Controller */
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+#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
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+#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val)
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+#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
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+#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR,val)
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+#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
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+#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR,val)
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+#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
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+#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT,val)
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+#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
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+#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT,val)
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+#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
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+#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY,val)
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+#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
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+#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY,val)
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+#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
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+#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR,val)
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+#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
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+#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR,val)
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+#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
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+#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT,val)
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+#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
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+#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT,val)
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+#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
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+#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS,val)
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+#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
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+#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP,val)
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+
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+#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
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+#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG,val)
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+#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
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+#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR,val)
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+#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
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+#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR,val)
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+#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
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+#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT,val)
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+#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
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+#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT,val)
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+#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
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+#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY,val)
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+#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
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+#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY,val)
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+#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
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+#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR,val)
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+#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
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+#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR,val)
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+#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
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+#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT,val)
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+#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
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+#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT,val)
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+#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
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+#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS,val)
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+#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
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+#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP,val)
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+
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+#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
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+#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG,val)
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+#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
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+#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR,val)
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+#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
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+#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR,val)
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+#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
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+#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT,val)
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+#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
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+#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT,val)
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+#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
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+#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY,val)
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+#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
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+#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY,val)
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+#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
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+#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR,val)
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+#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
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+#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR,val)
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+#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
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+#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT,val)
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+#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
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+#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT,val)
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+#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
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+#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS,val)
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+#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
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+#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP,val)
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+
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