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@@ -84,3 +84,16 @@
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#define MX27_JAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3e000)
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#define MX27_MAX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3f000)
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+#define MX27_AVIC_BASE_ADDR 0x10040000
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+
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+/* ROM patch */
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+#define MX27_ROMP_BASE_ADDR 0x10041000
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+
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+#define MX27_SAHB1_BASE_ADDR 0x80000000
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+#define MX27_SAHB1_SIZE SZ_1M
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+#define MX27_CSI_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x0000)
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+#define MX27_ATA_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x1000)
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+
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+/* Memory regions and CS */
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+#define MX27_SDRAM_BASE_ADDR 0xa0000000
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+#define MX27_CSD1_BASE_ADDR 0xb0000000
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