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@@ -1470,3 +1470,78 @@ ia64_pal_register_info (u64 info_request, u64 *reg_info_1, u64 *reg_info_2)
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struct ia64_pal_retval iprv;
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PAL_CALL(iprv, PAL_REGISTER_INFO, info_request, 0, 0);
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if (reg_info_1)
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+ *reg_info_1 = iprv.v0;
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+ if (reg_info_2)
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+ *reg_info_2 = iprv.v1;
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+ return iprv.status;
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+}
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+
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+typedef union pal_hints_u {
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+ unsigned long ph_data;
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+ struct {
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+ unsigned long si : 1,
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+ li : 1,
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+ reserved : 62;
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+ } pal_hints_s;
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+} pal_hints_u_t;
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+
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+/* Return information about the register stack and RSE for this processor
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+ * implementation.
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+ */
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+static inline long ia64_pal_rse_info(unsigned long *num_phys_stacked,
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+ pal_hints_u_t *hints)
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+{
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+ struct ia64_pal_retval iprv;
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+ PAL_CALL(iprv, PAL_RSE_INFO, 0, 0, 0);
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+ if (num_phys_stacked)
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+ *num_phys_stacked = iprv.v0;
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+ if (hints)
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+ hints->ph_data = iprv.v1;
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+ return iprv.status;
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+}
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+
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+/*
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+ * Set the current hardware resource sharing policy of the processor
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+ */
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+static inline s64
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+ia64_pal_set_hw_policy (u64 policy)
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+{
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+ struct ia64_pal_retval iprv;
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+ PAL_CALL(iprv, PAL_SET_HW_POLICY, policy, 0, 0);
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+ return iprv.status;
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+}
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+
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+/* Cause the processor to enter SHUTDOWN state, where prefetching and execution are
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+ * suspended, but cause cache and TLB coherency to be maintained.
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+ * This is usually called in IA-32 mode.
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+ */
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+static inline s64
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+ia64_pal_shutdown (void)
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+{
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+ struct ia64_pal_retval iprv;
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+ PAL_CALL(iprv, PAL_SHUTDOWN, 0, 0, 0);
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+ return iprv.status;
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+}
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+
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+/* Perform the second phase of processor self-test. */
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+static inline s64
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+ia64_pal_test_proc (u64 test_addr, u64 test_size, u64 attributes, u64 *self_test_state)
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+{
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+ struct ia64_pal_retval iprv;
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+ PAL_CALL(iprv, PAL_TEST_PROC, test_addr, test_size, attributes);
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+ if (self_test_state)
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+ *self_test_state = iprv.v0;
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+ return iprv.status;
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+}
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+
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+typedef union pal_version_u {
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+ u64 pal_version_val;
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+ struct {
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+ u64 pv_pal_b_rev : 8;
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+ u64 pv_pal_b_model : 8;
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+ u64 pv_reserved1 : 8;
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+ u64 pv_pal_vendor : 8;
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+ u64 pv_pal_a_rev : 8;
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+ u64 pv_pal_a_model : 8;
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+ u64 pv_reserved2 : 16;
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+ } pal_version_s;
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