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@@ -300,3 +300,47 @@ static struct clk pck0 = {
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static struct clk pck1 = {
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static struct clk pck1 = {
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.name = "pck1",
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.name = "pck1",
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.pmc_mask = AT91_PMC_PCK1,
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.pmc_mask = AT91_PMC_PCK1,
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+ .type = CLK_TYPE_PROGRAMMABLE,
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+ .id = 1,
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+};
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+
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+static void __init at91sam9g45_register_clocks(void)
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+{
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+ int i;
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+
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+ for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
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+ clk_register(periph_clocks[i]);
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+
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+ clkdev_add_table(periph_clocks_lookups,
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+ ARRAY_SIZE(periph_clocks_lookups));
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+ clkdev_add_table(usart_clocks_lookups,
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+ ARRAY_SIZE(usart_clocks_lookups));
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+
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+ if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11())
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+ clk_register(&vdec_clk);
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+
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+ clk_register(&pck0);
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+ clk_register(&pck1);
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+}
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+
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+/* --------------------------------------------------------------------
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+ * GPIO
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+ * -------------------------------------------------------------------- */
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+
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+static struct at91_gpio_bank at91sam9g45_gpio[] __initdata = {
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+ {
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+ .id = AT91SAM9G45_ID_PIOA,
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+ .regbase = AT91SAM9G45_BASE_PIOA,
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+ }, {
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+ .id = AT91SAM9G45_ID_PIOB,
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+ .regbase = AT91SAM9G45_BASE_PIOB,
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+ }, {
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+ .id = AT91SAM9G45_ID_PIOC,
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+ .regbase = AT91SAM9G45_BASE_PIOC,
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+ }, {
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+ .id = AT91SAM9G45_ID_PIODE,
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+ .regbase = AT91SAM9G45_BASE_PIOD,
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+ }, {
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+ .id = AT91SAM9G45_ID_PIODE,
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+ .regbase = AT91SAM9G45_BASE_PIOE,
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+ }
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