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@@ -169,3 +169,177 @@
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#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
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#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
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#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
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+#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
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+#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
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+#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
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+#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
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+#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
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+#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
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+#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
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+#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
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+#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
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+#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
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+#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
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+#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
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+#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
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+#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
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+#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
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+#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
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+#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
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+#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
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+#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
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+#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
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+#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
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+#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
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+#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
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+#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
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+#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
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+#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
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+#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
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+#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
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+#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
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+#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
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+#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
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+#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
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+#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
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+#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
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+#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
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+#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
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+#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
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+#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
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+
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+/* Asynchronous Memory Control Registers */
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+
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+#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
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+#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
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+#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
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+#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
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+#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
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+#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
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+#define bfin_read_EBIU_MBSCTL() bfin_read16(EBIU_MBSCTL)
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+#define bfin_write_EBIU_MBSCTL(val) bfin_write16(EBIU_MBSCTL, val)
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+#define bfin_read_EBIU_ARBSTAT() bfin_read32(EBIU_ARBSTAT)
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+#define bfin_write_EBIU_ARBSTAT(val) bfin_write32(EBIU_ARBSTAT, val)
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+#define bfin_read_EBIU_MODE() bfin_read32(EBIU_MODE)
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+#define bfin_write_EBIU_MODE(val) bfin_write32(EBIU_MODE, val)
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+#define bfin_read_EBIU_FCTL() bfin_read16(EBIU_FCTL)
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+#define bfin_write_EBIU_FCTL(val) bfin_write16(EBIU_FCTL, val)
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+
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+/* DDR Memory Control Registers */
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+
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+#define bfin_read_EBIU_DDRCTL0() bfin_read32(EBIU_DDRCTL0)
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+#define bfin_write_EBIU_DDRCTL0(val) bfin_write32(EBIU_DDRCTL0, val)
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+#define bfin_read_EBIU_DDRCTL1() bfin_read32(EBIU_DDRCTL1)
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+#define bfin_write_EBIU_DDRCTL1(val) bfin_write32(EBIU_DDRCTL1, val)
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+#define bfin_read_EBIU_DDRCTL2() bfin_read32(EBIU_DDRCTL2)
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+#define bfin_write_EBIU_DDRCTL2(val) bfin_write32(EBIU_DDRCTL2, val)
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+#define bfin_read_EBIU_DDRCTL3() bfin_read32(EBIU_DDRCTL3)
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+#define bfin_write_EBIU_DDRCTL3(val) bfin_write32(EBIU_DDRCTL3, val)
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+#define bfin_read_EBIU_DDRQUE() bfin_read32(EBIU_DDRQUE)
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+#define bfin_write_EBIU_DDRQUE(val) bfin_write32(EBIU_DDRQUE, val)
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+#define bfin_read_EBIU_ERRADD() bfin_read32(EBIU_ERRADD)
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+#define bfin_write_EBIU_ERRADD(val) bfin_write32(EBIU_ERRADD, val)
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+#define bfin_read_EBIU_ERRMST() bfin_read16(EBIU_ERRMST)
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+#define bfin_write_EBIU_ERRMST(val) bfin_write16(EBIU_ERRMST, val)
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+#define bfin_read_EBIU_RSTCTL() bfin_read16(EBIU_RSTCTL)
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+#define bfin_write_EBIU_RSTCTL(val) bfin_write16(EBIU_RSTCTL, val)
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+
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+/* DDR BankRead and Write Count Registers */
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+
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+#define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0)
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+#define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val)
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+#define bfin_read_EBIU_DDRBRC1() bfin_read32(EBIU_DDRBRC1)
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+#define bfin_write_EBIU_DDRBRC1(val) bfin_write32(EBIU_DDRBRC1, val)
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+#define bfin_read_EBIU_DDRBRC2() bfin_read32(EBIU_DDRBRC2)
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+#define bfin_write_EBIU_DDRBRC2(val) bfin_write32(EBIU_DDRBRC2, val)
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+#define bfin_read_EBIU_DDRBRC3() bfin_read32(EBIU_DDRBRC3)
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+#define bfin_write_EBIU_DDRBRC3(val) bfin_write32(EBIU_DDRBRC3, val)
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+#define bfin_read_EBIU_DDRBRC4() bfin_read32(EBIU_DDRBRC4)
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+#define bfin_write_EBIU_DDRBRC4(val) bfin_write32(EBIU_DDRBRC4, val)
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+#define bfin_read_EBIU_DDRBRC5() bfin_read32(EBIU_DDRBRC5)
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+#define bfin_write_EBIU_DDRBRC5(val) bfin_write32(EBIU_DDRBRC5, val)
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+#define bfin_read_EBIU_DDRBRC6() bfin_read32(EBIU_DDRBRC6)
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+#define bfin_write_EBIU_DDRBRC6(val) bfin_write32(EBIU_DDRBRC6, val)
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+#define bfin_read_EBIU_DDRBRC7() bfin_read32(EBIU_DDRBRC7)
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+#define bfin_write_EBIU_DDRBRC7(val) bfin_write32(EBIU_DDRBRC7, val)
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+#define bfin_read_EBIU_DDRBWC0() bfin_read32(EBIU_DDRBWC0)
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+#define bfin_write_EBIU_DDRBWC0(val) bfin_write32(EBIU_DDRBWC0, val)
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+#define bfin_read_EBIU_DDRBWC1() bfin_read32(EBIU_DDRBWC1)
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+#define bfin_write_EBIU_DDRBWC1(val) bfin_write32(EBIU_DDRBWC1, val)
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+#define bfin_read_EBIU_DDRBWC2() bfin_read32(EBIU_DDRBWC2)
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+#define bfin_write_EBIU_DDRBWC2(val) bfin_write32(EBIU_DDRBWC2, val)
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+#define bfin_read_EBIU_DDRBWC3() bfin_read32(EBIU_DDRBWC3)
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+#define bfin_write_EBIU_DDRBWC3(val) bfin_write32(EBIU_DDRBWC3, val)
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+#define bfin_read_EBIU_DDRBWC4() bfin_read32(EBIU_DDRBWC4)
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+#define bfin_write_EBIU_DDRBWC4(val) bfin_write32(EBIU_DDRBWC4, val)
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+#define bfin_read_EBIU_DDRBWC5() bfin_read32(EBIU_DDRBWC5)
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+#define bfin_write_EBIU_DDRBWC5(val) bfin_write32(EBIU_DDRBWC5, val)
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+#define bfin_read_EBIU_DDRBWC6() bfin_read32(EBIU_DDRBWC6)
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+#define bfin_write_EBIU_DDRBWC6(val) bfin_write32(EBIU_DDRBWC6, val)
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+#define bfin_read_EBIU_DDRBWC7() bfin_read32(EBIU_DDRBWC7)
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+#define bfin_write_EBIU_DDRBWC7(val) bfin_write32(EBIU_DDRBWC7, val)
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+#define bfin_read_EBIU_DDRACCT() bfin_read32(EBIU_DDRACCT)
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+#define bfin_write_EBIU_DDRACCT(val) bfin_write32(EBIU_DDRACCT, val)
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+#define bfin_read_EBIU_DDRTACT() bfin_read32(EBIU_DDRTACT)
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+#define bfin_write_EBIU_DDRTACT(val) bfin_write32(EBIU_DDRTACT, val)
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+#define bfin_read_EBIU_DDRARCT() bfin_read32(EBIU_DDRARCT)
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+#define bfin_write_EBIU_DDRARCT(val) bfin_write32(EBIU_DDRARCT, val)
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+#define bfin_read_EBIU_DDRGC0() bfin_read32(EBIU_DDRGC0)
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+#define bfin_write_EBIU_DDRGC0(val) bfin_write32(EBIU_DDRGC0, val)
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+#define bfin_read_EBIU_DDRGC1() bfin_read32(EBIU_DDRGC1)
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+#define bfin_write_EBIU_DDRGC1(val) bfin_write32(EBIU_DDRGC1, val)
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+#define bfin_read_EBIU_DDRGC2() bfin_read32(EBIU_DDRGC2)
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+#define bfin_write_EBIU_DDRGC2(val) bfin_write32(EBIU_DDRGC2, val)
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+#define bfin_read_EBIU_DDRGC3() bfin_read32(EBIU_DDRGC3)
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+#define bfin_write_EBIU_DDRGC3(val) bfin_write32(EBIU_DDRGC3, val)
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+#define bfin_read_EBIU_DDRMCEN() bfin_read32(EBIU_DDRMCEN)
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+#define bfin_write_EBIU_DDRMCEN(val) bfin_write32(EBIU_DDRMCEN, val)
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+#define bfin_read_EBIU_DDRMCCL() bfin_read32(EBIU_DDRMCCL)
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+#define bfin_write_EBIU_DDRMCCL(val) bfin_write32(EBIU_DDRMCCL, val)
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+
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+/* DMAC0 Registers */
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+
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+#define bfin_read_DMAC0_TC_PER() bfin_read16(DMAC0_TC_PER)
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+#define bfin_write_DMAC0_TC_PER(val) bfin_write16(DMAC0_TC_PER, val)
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+#define bfin_read_DMAC0_TC_CNT() bfin_read16(DMAC0_TC_CNT)
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+#define bfin_write_DMAC0_TC_CNT(val) bfin_write16(DMAC0_TC_CNT, val)
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+
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+/* DMA Channel 0 Registers */
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+
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+#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
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+#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
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+#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
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+#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
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+#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
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+#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
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+#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
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+#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
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+#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
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+#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
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+#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
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+#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
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+#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
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+#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
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+#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
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+#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
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+#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
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+#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
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+#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
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+#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
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+#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
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+#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
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+#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
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+#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
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+#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
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+#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
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+
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+/* DMA Channel 1 Registers */
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+
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+#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
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+#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
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+#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
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+#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
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+#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
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+#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
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+#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
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+#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
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朱涛