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@@ -290,3 +290,71 @@
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#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
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#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
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#define nEP4_TX 0x0
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#define nEP4_TX 0x0
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#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
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#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
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+#define nEP5_TX 0x0
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+#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
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+#define nEP6_TX 0x0
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+#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
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+#define nEP7_TX 0x0
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+
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+/* Bit masks for USB_INTRRX */
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+
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+#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
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+#define nEP1_RX 0x0
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+#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
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+#define nEP2_RX 0x0
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+#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
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+#define nEP3_RX 0x0
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+#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
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+#define nEP4_RX 0x0
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+#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
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+#define nEP5_RX 0x0
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+#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
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+#define nEP6_RX 0x0
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+#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
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+#define nEP7_RX 0x0
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+
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+/* Bit masks for USB_INTRTXE */
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+
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+#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
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+#define nEP0_TX_E 0x0
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+#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
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+#define nEP1_TX_E 0x0
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+#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
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+#define nEP2_TX_E 0x0
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+#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
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+#define nEP3_TX_E 0x0
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+#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
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+#define nEP4_TX_E 0x0
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+#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
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+#define nEP5_TX_E 0x0
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+#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
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+#define nEP6_TX_E 0x0
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+#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
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+#define nEP7_TX_E 0x0
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+
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+/* Bit masks for USB_INTRRXE */
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+
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+#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
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+#define nEP1_RX_E 0x0
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+#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
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+#define nEP2_RX_E 0x0
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+#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
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+#define nEP3_RX_E 0x0
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+#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
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+#define nEP4_RX_E 0x0
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+#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
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+#define nEP5_RX_E 0x0
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+#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
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+#define nEP6_RX_E 0x0
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+#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
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+#define nEP7_RX_E 0x0
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+
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+/* Bit masks for USB_INTRUSB */
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+
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+#define SUSPEND_B 0x1 /* Suspend indicator */
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+#define nSUSPEND_B 0x0
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+#define RESUME_B 0x2 /* Resume indicator */
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+#define nRESUME_B 0x0
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+#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
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+#define nRESET_OR_BABLE_B 0x0
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+#define SOF_B 0x8 /* Start of frame */
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