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				@@ -101,3 +101,35 @@ 
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				 #define OMAP3430_GRPSEL_MCSPI3_MASK			(1 << 20) 
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				 #define OMAP3430_GRPSEL_MCSPI2_MASK			(1 << 19) 
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				 #define OMAP3430_GRPSEL_MCSPI1_MASK			(1 << 18) 
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				+#define OMAP3430_GRPSEL_I2C3_SHIFT			17 
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				+#define OMAP3430_GRPSEL_I2C3_MASK			(1 << 17) 
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				+#define OMAP3430_GRPSEL_I2C2_SHIFT			16 
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				+#define OMAP3430_GRPSEL_I2C2_MASK			(1 << 16) 
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				+#define OMAP3430_GRPSEL_I2C1_SHIFT			15 
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				+#define OMAP3430_GRPSEL_I2C1_MASK			(1 << 15) 
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				+#define OMAP3430_GRPSEL_UART2_MASK			(1 << 14) 
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				+#define OMAP3430_GRPSEL_UART1_MASK			(1 << 13) 
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				+#define OMAP3430_GRPSEL_GPT11_MASK			(1 << 12) 
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				+#define OMAP3430_GRPSEL_GPT10_MASK			(1 << 11) 
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				+#define OMAP3430_GRPSEL_MCBSP5_MASK			(1 << 10) 
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				+#define OMAP3430_GRPSEL_MCBSP1_MASK			(1 << 9) 
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				+#define OMAP3430_GRPSEL_HSOTGUSB_MASK			(1 << 4) 
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				+#define OMAP3430_GRPSEL_D2D_MASK			(1 << 3) 
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				+ 
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				+/* 
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				+ * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, 
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				+ * PM_PWSTCTRL_PER shared bits 
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				+ */ 
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				+#define OMAP3430_MEMONSTATE_SHIFT			16 
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				+#define OMAP3430_MEMONSTATE_MASK			(0x3 << 16) 
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				+#define OMAP3430_MEMRETSTATE_MASK			(1 << 8) 
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				+ 
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				+/* PM_MPUGRPSEL_PER, PM_IVA2GRPSEL_PER shared bits */ 
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				+#define OMAP3630_GRPSEL_UART4_MASK			(1 << 18) 
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				+#define OMAP3430_GRPSEL_GPIO6_MASK			(1 << 17) 
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				+#define OMAP3430_GRPSEL_GPIO5_MASK			(1 << 16) 
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				+#define OMAP3430_GRPSEL_GPIO4_MASK			(1 << 15) 
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				+#define OMAP3430_GRPSEL_GPIO3_MASK			(1 << 14) 
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				+#define OMAP3430_GRPSEL_GPIO2_MASK			(1 << 13) 
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				+#define OMAP3430_GRPSEL_UART3_MASK			(1 << 11) 
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				+#define OMAP3430_GRPSEL_GPT9_MASK			(1 << 10) 
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