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@@ -148,3 +148,86 @@ do { \
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#define VCC_RCC_CSM_SHIFT 13
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#define VCC_RCC_ES 0x00008000 /* capture start polarity */
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#define VCC_RCC_ES_NEG 0x00000000 /* - negative edge */
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+#define VCC_RCC_ES_POS 0x00008000 /* - positive edge */
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+#define VCC_RCC_IFI 0x00080000 /* inferlace field evaluation reverse */
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+#define VCC_RCC_FDTS 0x00300000 /* interlace field start */
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+#define VCC_RCC_FDTS_3_8 0x00000000 /* - 3/8 of horizontal entire cycle */
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+#define VCC_RCC_FDTS_1_4 0x00100000 /* - 1/4 of horizontal entire cycle */
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+#define VCC_RCC_FDTS_7_16 0x00200000 /* - 7/16 of horizontal entire cycle */
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+#define VCC_RCC_FDTS_SHIFT 20
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+#define VCC_RCC_MOV 0x00400000 /* test bit - always set to 1 */
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+#define VCC_RCC_STP 0x00800000 /* request video capture stop */
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+#define VCC_RCC_TO 0x01000000 /* input during top-field only */
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+
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+#define VCC_RIS_VSYNC 0x01000000 /* VSYNC interrupt */
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+#define VCC_RIS_OV 0x02000000 /* overflow interrupt */
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+#define VCC_RIS_BOTTOM 0x08000000 /* interlace bottom field */
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+#define VCC_RIS_STARTED 0x10000000 /* capture started */
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+
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+/*
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+ * I2C
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+ */
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+#define MB93493_I2C_BSR 0x340 /* bus status */
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+#define MB93493_I2C_BCR 0x344 /* bus control */
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+#define MB93493_I2C_CCR 0x348 /* clock control */
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+#define MB93493_I2C_ADR 0x34c /* address */
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+#define MB93493_I2C_DTR 0x350 /* data */
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+#define MB93493_I2C_BC2R 0x35c /* bus control 2 */
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+
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+#define __addr_MB93493_I2C(port,X) (__region_CS3 + MB93493_I2C_##X + ((port)*0x20))
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+#define __get_MB93493_I2C(port,X) __get_MB93493(MB93493_I2C_##X + ((port)*0x20))
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+#define __set_MB93493_I2C(port,X,V) __set_MB93493(MB93493_I2C_##X + ((port)*0x20), (V))
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+
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+#define I2C_BSR_BB (1 << 7)
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+
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+/*
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+ * audio controller (I2S) registers
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+ */
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+#define __get_MB93493_I2S(X) __get_MB93493(MB93493_I2S_##X)
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+#define __set_MB93493_I2S(X,V) __set_MB93493(MB93493_I2S_##X, (V))
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+
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+#define MB93493_I2S_ALDR 0x300 /* L-channel data */
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+#define MB93493_I2S_ARDR 0x304 /* R-channel data */
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+#define MB93493_I2S_APDR 0x308 /* 16-bit packed data */
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+#define MB93493_I2S_AISTR 0x310 /* status */
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+#define MB93493_I2S_AICR 0x314 /* control */
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+
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+#define __addr_MB93493_I2S_ALDR(X) (__region_CS3 + MB93493_I2S_ALDR + (X))
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+#define __addr_MB93493_I2S_ARDR(X) (__region_CS3 + MB93493_I2S_ARDR + (X))
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+#define __addr_MB93493_I2S_APDR(X) (__region_CS3 + MB93493_I2S_APDR + (X))
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+#define __addr_MB93493_I2S_ADR(X) (__region_CS3 + 0x320 + (X))
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+
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+#define I2S_AISTR_OTST 0x00000003 /* status of output data transfer */
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+#define I2S_AISTR_OTR 0x00000010 /* output transfer request pending */
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+#define I2S_AISTR_OUR 0x00000020 /* output FIFO underrun detected */
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+#define I2S_AISTR_OOR 0x00000040 /* output FIFO overrun detected */
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+#define I2S_AISTR_ODS 0x00000100 /* output DMA transfer size */
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+#define I2S_AISTR_ODE 0x00000400 /* output DMA transfer request enable */
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+#define I2S_AISTR_OTRIE 0x00001000 /* output transfer request interrupt enable */
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+#define I2S_AISTR_OURIE 0x00002000 /* output FIFO underrun interrupt enable */
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+#define I2S_AISTR_OORIE 0x00004000 /* output FIFO overrun interrupt enable */
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+#define I2S_AISTR__OUT_MASK 0x00007570
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+#define I2S_AISTR_ITST 0x00030000 /* status of input data transfer */
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+#define I2S_AISTR_ITST_SHIFT 16
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+#define I2S_AISTR_ITR 0x00100000 /* input transfer request pending */
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+#define I2S_AISTR_IUR 0x00200000 /* input FIFO underrun detected */
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+#define I2S_AISTR_IOR 0x00400000 /* input FIFO overrun detected */
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+#define I2S_AISTR_IDS 0x01000000 /* input DMA transfer size */
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+#define I2S_AISTR_IDE 0x04000000 /* input DMA transfer request enable */
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+#define I2S_AISTR_ITRIE 0x10000000 /* input transfer request interrupt enable */
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+#define I2S_AISTR_IURIE 0x20000000 /* input FIFO underrun interrupt enable */
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+#define I2S_AISTR_IORIE 0x40000000 /* input FIFO overrun interrupt enable */
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+#define I2S_AISTR__IN_MASK 0x75700000
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+
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+#define I2S_AICR_MI 0x00000001 /* mono input requested */
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+#define I2S_AICR_AMI 0x00000002 /* relation between LRCKI/FS1 and SDI */
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+#define I2S_AICR_LRI 0x00000004 /* function of LRCKI pin */
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+#define I2S_AICR_SDMI 0x00000070 /* format of input audio data */
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+#define I2S_AICR_SDMI_SHIFT 4
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+#define I2S_AICR_CLI 0x00000080 /* input FIFO clearing control */
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+#define I2S_AICR_IM 0x00000300 /* input state control */
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+#define I2S_AICR_IM_SHIFT 8
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+#define I2S_AICR__IN_MASK 0x000003f7
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+#define I2S_AICR_MO 0x00001000 /* mono output requested */
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+#define I2S_AICR_AMO 0x00002000 /* relation between LRCKO/FS0 and SDO */
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+#define I2S_AICR_AMO_SHIFT 13
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