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+/*
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+ * OMAP2420 clock data
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+ *
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+ * Copyright (C) 2005-2012 Texas Instruments, Inc.
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+ * Copyright (C) 2004-2011 Nokia Corporation
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+ *
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+ * Contacts:
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+ * Richard Woodruff <r-woodruff2@ti.com>
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+ * Paul Walmsley
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+ * Updated to COMMON clk format by Rajendra Nayak <rnayak@ti.com>
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/io.h>
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+#include <linux/clk.h>
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+#include <linux/clk-private.h>
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+#include <linux/list.h>
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+
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+#include "soc.h"
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+#include "iomap.h"
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+#include "clock.h"
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+#include "clock2xxx.h"
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+#include "opp2xxx.h"
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+#include "cm2xxx.h"
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+#include "prm2xxx.h"
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+#include "prm-regbits-24xx.h"
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+#include "cm-regbits-24xx.h"
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+#include "sdrc.h"
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+#include "control.h"
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+
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+#define OMAP_CM_REGADDR OMAP2420_CM_REGADDR
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+
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+/*
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+ * 2420 clock tree.
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+ *
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+ * NOTE:In many cases here we are assigning a 'default' parent. In
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+ * many cases the parent is selectable. The set parent calls will
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+ * also switch sources.
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+ *
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+ * Several sources are given initial rates which may be wrong, this will
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+ * be fixed up in the init func.
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+ *
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+ * Things are broadly separated below by clock domains. It is
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+ * noteworthy that most peripherals have dependencies on multiple clock
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+ * domains. Many get their interface clocks from the L4 domain, but get
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+ * functional clocks from fixed sources or other core domain derived
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+ * clocks.
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+ */
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+
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+DEFINE_CLK_FIXED_RATE(alt_ck, CLK_IS_ROOT, 54000000, 0x0);
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+
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+DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0);
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+
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+DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0);
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+
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+static struct clk osc_ck;
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+
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+static const struct clk_ops osc_ck_ops = {
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+ .recalc_rate = &omap2_osc_clk_recalc,
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+};
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+
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+static struct clk_hw_omap osc_ck_hw = {
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+ .hw = {
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+ .clk = &osc_ck,
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+ },
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+};
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+
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+static struct clk osc_ck = {
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+ .name = "osc_ck",
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+ .ops = &osc_ck_ops,
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+ .hw = &osc_ck_hw.hw,
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+ .flags = CLK_IS_ROOT,
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+};
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+
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+DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0);
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+
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+static struct clk sys_ck;
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+
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+static const char *sys_ck_parent_names[] = {
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+ "osc_ck",
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+};
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+
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+static const struct clk_ops sys_ck_ops = {
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+ .init = &omap2_init_clk_clkdm,
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+ .recalc_rate = &omap2xxx_sys_clk_recalc,
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+};
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+
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+DEFINE_STRUCT_CLK_HW_OMAP(sys_ck, "wkup_clkdm");
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+DEFINE_STRUCT_CLK(sys_ck, sys_ck_parent_names, sys_ck_ops);
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+
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+static struct dpll_data dpll_dd = {
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+ .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
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+ .mult_mask = OMAP24XX_DPLL_MULT_MASK,
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+ .div1_mask = OMAP24XX_DPLL_DIV_MASK,
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+ .clk_bypass = &sys_ck,
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+ .clk_ref = &sys_ck,
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