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+/*
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+ * bfin_serial.h - Blackfin UART/Serial definitions
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+ *
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+ * Copyright 2006-2010 Analog Devices Inc.
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+ *
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+ * Licensed under the GPL-2 or later.
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+ */
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+
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+#ifndef __BFIN_ASM_SERIAL_H__
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+#define __BFIN_ASM_SERIAL_H__
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+
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+#include <linux/serial_core.h>
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+#include <linux/spinlock.h>
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+#include <mach/anomaly.h>
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+#include <mach/bfin_serial.h>
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+
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+#if defined(CONFIG_BFIN_UART0_CTSRTS) || \
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+ defined(CONFIG_BFIN_UART1_CTSRTS) || \
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+ defined(CONFIG_BFIN_UART2_CTSRTS) || \
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+ defined(CONFIG_BFIN_UART3_CTSRTS)
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+# if defined(BFIN_UART_BF54X_STYLE) || defined(BFIN_UART_BF60X_STYLE)
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+# define CONFIG_SERIAL_BFIN_HARD_CTSRTS
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+# else
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+# define CONFIG_SERIAL_BFIN_CTSRTS
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+# endif
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+#endif
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+
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+struct circ_buf;
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+struct timer_list;
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+struct work_struct;
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+
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+struct bfin_serial_port {
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+ struct uart_port port;
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+ unsigned int old_status;
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+ int tx_irq;
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+ int rx_irq;
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+ int status_irq;
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+#ifndef BFIN_UART_BF54X_STYLE
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+ unsigned int lsr;
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+#endif
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+#ifdef CONFIG_SERIAL_BFIN_DMA
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+ int tx_done;
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+ int tx_count;
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+ struct circ_buf rx_dma_buf;
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+ struct timer_list rx_dma_timer;
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+ int rx_dma_nrows;
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+ spinlock_t rx_lock;
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+ unsigned int tx_dma_channel;
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+ unsigned int rx_dma_channel;
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+ struct work_struct tx_dma_workqueue;
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+#elif ANOMALY_05000363
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+ unsigned int anomaly_threshold;
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+#endif
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+#if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
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+ defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
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+ int cts_pin;
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+ int rts_pin;
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+#endif
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+};
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+
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+#ifdef BFIN_UART_BF60X_STYLE
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+
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+/* UART_CTL Masks */
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+#define UCEN 0x1 /* Enable UARTx Clocks */
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+#define LOOP_ENA 0x2 /* Loopback Mode Enable */
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+#define UMOD_MDB 0x10 /* Enable MDB Mode */
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+#define UMOD_IRDA 0x20 /* Enable IrDA Mode */
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+#define UMOD_MASK 0x30 /* Uart Mode Mask */
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+#define WLS(x) (((x-5) & 0x03) << 8) /* Word Length Select */
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+#define WLS_MASK 0x300 /* Word length Select Mask */
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+#define WLS_OFFSET 8 /* Word length Select Offset */
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+#define STB 0x1000 /* Stop Bits */
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+#define STBH 0x2000 /* Half Stop Bits */
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+#define PEN 0x4000 /* Parity Enable */
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+#define EPS 0x8000 /* Even Parity Select */
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+#define STP 0x10000 /* Stick Parity */
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+#define FPE 0x20000 /* Force Parity Error On Transmit */
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+#define FFE 0x40000 /* Force Framing Error On Transmit */
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+#define SB 0x80000 /* Set Break */
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+#define LCR_MASK (SB | STP | EPS | PEN | STB | WLS_MASK)
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+#define FCPOL 0x400000 /* Flow Control Pin Polarity */
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+#define RPOLC 0x800000 /* IrDA RX Polarity Change */
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+#define TPOLC 0x1000000 /* IrDA TX Polarity Change */
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+#define MRTS 0x2000000 /* Manual Request To Send */
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+#define XOFF 0x4000000 /* Transmitter Off */
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+#define ARTS 0x8000000 /* Automatic Request To Send */
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+#define ACTS 0x10000000 /* Automatic Clear To Send */
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+#define RFIT 0x20000000 /* Receive FIFO IRQ Threshold */
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+#define RFRT 0x40000000 /* Receive FIFO RTS Threshold */
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+
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+/* UART_STAT Masks */
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+#define DR 0x01 /* Data Ready */
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+#define OE 0x02 /* Overrun Error */
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+#define PE 0x04 /* Parity Error */
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+#define FE 0x08 /* Framing Error */
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+#define BI 0x10 /* Break Interrupt */
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+#define THRE 0x20 /* THR Empty */
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+#define TEMT 0x80 /* TSR and UART_THR Empty */
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+#define TFI 0x100 /* Transmission Finished Indicator */
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+
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+#define ASTKY 0x200 /* Address Sticky */
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+#define ADDR 0x400 /* Address bit status */
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+#define RO 0x800 /* Reception Ongoing */
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+#define SCTS 0x1000 /* Sticky CTS */
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+#define CTS 0x10000 /* Clear To Send */
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+#define RFCS 0x20000 /* Receive FIFO Count Status */
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+
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+/* UART_CLOCK Masks */
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+#define EDBO 0x80000000 /* Enable Devide by One */
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+
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+#else /* BFIN_UART_BF60X_STYLE */
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+
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+/* UART_LCR Masks */
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+#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
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+#define WLS_MASK 0x03 /* Word length Select Mask */
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+#define WLS_OFFSET 0 /* Word length Select Offset */
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+#define STB 0x04 /* Stop Bits */
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+#define PEN 0x08 /* Parity Enable */
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+#define EPS 0x10 /* Even Parity Select */
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+#define STP 0x20 /* Stick Parity */
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+#define SB 0x40 /* Set Break */
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+#define DLAB 0x80 /* Divisor Latch Access */
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+#define LCR_MASK (SB | STP | EPS | PEN | STB | WLS_MASK)
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+
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+/* UART_LSR Masks */
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+#define DR 0x01 /* Data Ready */
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+#define OE 0x02 /* Overrun Error */
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+#define PE 0x04 /* Parity Error */
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+#define FE 0x08 /* Framing Error */
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+#define BI 0x10 /* Break Interrupt */
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+#define THRE 0x20 /* THR Empty */
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+#define TEMT 0x40 /* TSR and UART_THR Empty */
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+#define TFI 0x80 /* Transmission Finished Indicator */
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+
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+/* UART_MCR Masks */
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+#define XOFF 0x01 /* Transmitter Off */
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+#define MRTS 0x02 /* Manual Request To Send */
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+#define RFIT 0x04 /* Receive FIFO IRQ Threshold */
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+#define RFRT 0x08 /* Receive FIFO RTS Threshold */
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+#define LOOP_ENA 0x10 /* Loopback Mode Enable */
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+#define FCPOL 0x20 /* Flow Control Pin Polarity */
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+#define ARTS 0x40 /* Automatic Request To Send */
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+#define ACTS 0x80 /* Automatic Clear To Send */
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+
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+/* UART_MSR Masks */
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+#define SCTS 0x01 /* Sticky CTS */
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+#define CTS 0x10 /* Clear To Send */
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+#define RFCS 0x20 /* Receive FIFO Count Status */
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+
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+/* UART_GCTL Masks */
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+#define UCEN 0x01 /* Enable UARTx Clocks */
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+#define UMOD_IRDA 0x02 /* Enable IrDA Mode */
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+#define UMOD_MASK 0x02 /* Uart Mode Mask */
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+#define TPOLC 0x04 /* IrDA TX Polarity Change */
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+#define RPOLC 0x08 /* IrDA RX Polarity Change */
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+#define FPE 0x10 /* Force Parity Error On Transmit */
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+#define FFE 0x20 /* Force Framing Error On Transmit */
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+
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+#endif /* BFIN_UART_BF60X_STYLE */
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+
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+/* UART_IER Masks */
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+#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
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