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@@ -336,3 +336,70 @@
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* System Controller interrupt controller base is
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* System Controller interrupt controller base is
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*
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*
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* INTEGRATOR_IC_BASE + (header_number << 6)
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* INTEGRATOR_IC_BASE + (header_number << 6)
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+ *
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+ * Core Module interrupt controller base is
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+ *
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+ * INTEGRATOR_HDR_IC
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+ *
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+ */
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+#define IRQ_STATUS 0
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+#define IRQ_RAW_STATUS 0x04
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+#define IRQ_ENABLE 0x08
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+#define IRQ_ENABLE_SET 0x08
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+#define IRQ_ENABLE_CLEAR 0x0C
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+
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+#define INT_SOFT_SET 0x10
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+#define INT_SOFT_CLEAR 0x14
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+
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+#define FIQ_STATUS 0x20
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+#define FIQ_RAW_STATUS 0x24
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+#define FIQ_ENABLE 0x28
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+#define FIQ_ENABLE_SET 0x28
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+#define FIQ_ENABLE_CLEAR 0x2C
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+
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+
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+/* ------------------------------------------------------------------------
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+ * Interrupts
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+ * ------------------------------------------------------------------------
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+ *
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+ *
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+ * Each Core Module has two interrupts controllers, one on the core module
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+ * itself and one in the system controller on the motherboard. The
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+ * READ_INT macro in target.s reads both interrupt controllers and returns
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+ * a 32 bit bitmask, bits 0 to 23 are interrupts from the system controller
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+ * and bits 24 to 31 are from the core module.
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+ *
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+ * The following definitions relate to the bitmask returned by READ_INT.
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+ *
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+ */
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+
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+/* ------------------------------------------------------------------------
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+ * LED's
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+ * ------------------------------------------------------------------------
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+ *
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+ */
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+#define GREEN_LED 0x01
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+#define YELLOW_LED 0x02
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+#define RED_LED 0x04
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+#define GREEN_LED_2 0x08
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+#define ALL_LEDS 0x0F
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+
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+#define LED_BANK INTEGRATOR_DBG_LEDS
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+
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+/*
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+ * Timer definitions
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+ *
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+ * Only use timer 1 & 2
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+ * (both run at 24MHz and will need the clock divider set to 16).
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+ *
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+ * Timer 0 runs at bus frequency
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+ */
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+
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+#define INTEGRATOR_TIMER0_BASE INTEGRATOR_CT_BASE
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+#define INTEGRATOR_TIMER1_BASE (INTEGRATOR_CT_BASE + 0x100)
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+#define INTEGRATOR_TIMER2_BASE (INTEGRATOR_CT_BASE + 0x200)
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+
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+#define INTEGRATOR_CSR_BASE 0x10000000
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+#define INTEGRATOR_CSR_SIZE 0x10000000
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+
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+#endif
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