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@@ -74,3 +74,130 @@ MUX_CFG_7XX("SPI_7XX_6", 9, 5, 0, 4, 0, 0)
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/* UART pins */
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MUX_CFG_7XX("UART_7XX_1", 3, 21, 0, 20, 0, 0)
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MUX_CFG_7XX("UART_7XX_2", 8, 1, 6, 0, 0, 0)
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+};
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+#define OMAP7XX_PINS_SZ ARRAY_SIZE(omap7xx_pins)
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+#else
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+#define omap7xx_pins NULL
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+#define OMAP7XX_PINS_SZ 0
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+#endif /* CONFIG_ARCH_OMAP730 || CONFIG_ARCH_OMAP850 */
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+
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+#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
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+static struct pin_config __initdata_or_module omap1xxx_pins[] = {
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+/*
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+ * description mux mode mux pull pull pull pu_pd pu dbg
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+ * reg offset mode reg bit ena reg
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+ */
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+MUX_CFG("UART1_TX", 9, 21, 1, 2, 3, 0, NA, 0, 0)
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+MUX_CFG("UART1_RTS", 9, 12, 1, 2, 0, 0, NA, 0, 0)
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+
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+/* UART2 (COM_UART_GATING), conflicts with USB2 */
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+MUX_CFG("UART2_TX", C, 27, 1, 3, 3, 0, NA, 0, 0)
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+MUX_CFG("UART2_RX", C, 18, 0, 3, 1, 1, NA, 0, 0)
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+MUX_CFG("UART2_CTS", C, 21, 0, 3, 1, 1, NA, 0, 0)
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+MUX_CFG("UART2_RTS", C, 24, 1, 3, 2, 0, NA, 0, 0)
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+
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+/* UART3 (GIGA_UART_GATING) */
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+MUX_CFG("UART3_TX", 6, 0, 1, 0, 30, 0, NA, 0, 0)
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+MUX_CFG("UART3_RX", 6, 3, 0, 0, 31, 1, NA, 0, 0)
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+MUX_CFG("UART3_CTS", 5, 12, 2, 0, 24, 0, NA, 0, 0)
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+MUX_CFG("UART3_RTS", 5, 15, 2, 0, 25, 0, NA, 0, 0)
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+MUX_CFG("UART3_CLKREQ", 9, 27, 0, 2, 5, 0, NA, 0, 0)
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+MUX_CFG("UART3_BCLK", A, 0, 0, 2, 6, 0, NA, 0, 0)
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+MUX_CFG("Y15_1610_UART3_RTS", A, 0, 1, 2, 6, 0, NA, 0, 0)
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+
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+/* PWT & PWL, conflicts with UART3 */
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+MUX_CFG("PWT", 6, 0, 2, 0, 30, 0, NA, 0, 0)
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+MUX_CFG("PWL", 6, 3, 1, 0, 31, 1, NA, 0, 0)
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+
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+/* USB internal master generic */
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+MUX_CFG("R18_USB_VBUS", 7, 9, 2, 1, 11, 0, NA, 0, 1)
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+MUX_CFG("R18_1510_USB_GPIO0", 7, 9, 0, 1, 11, 1, NA, 0, 1)
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+/* works around erratum: W4_USB_PUEN and W4_USB_PUDIS are switched! */
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+MUX_CFG("W4_USB_PUEN", D, 3, 3, 3, 5, 1, NA, 0, 1)
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+MUX_CFG("W4_USB_CLKO", D, 3, 1, 3, 5, 0, NA, 0, 1)
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+MUX_CFG("W4_USB_HIGHZ", D, 3, 4, 3, 5, 0, 3, 0, 1)
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+MUX_CFG("W4_GPIO58", D, 3, 7, 3, 5, 0, 3, 0, 1)
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+
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+/* USB1 master */
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+MUX_CFG("USB1_SUSP", 8, 27, 2, 1, 27, 0, NA, 0, 1)
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+MUX_CFG("USB1_SE0", 9, 0, 2, 1, 28, 0, NA, 0, 1)
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+MUX_CFG("W13_1610_USB1_SE0", 9, 0, 4, 1, 28, 0, NA, 0, 1)
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+MUX_CFG("USB1_TXEN", 9, 3, 2, 1, 29, 0, NA, 0, 1)
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+MUX_CFG("USB1_TXD", 9, 24, 1, 2, 4, 0, NA, 0, 1)
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+MUX_CFG("USB1_VP", A, 3, 1, 2, 7, 0, NA, 0, 1)
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+MUX_CFG("USB1_VM", A, 6, 1, 2, 8, 0, NA, 0, 1)
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+MUX_CFG("USB1_RCV", A, 9, 1, 2, 9, 0, NA, 0, 1)
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+MUX_CFG("USB1_SPEED", A, 12, 2, 2, 10, 0, NA, 0, 1)
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+MUX_CFG("R13_1610_USB1_SPEED", A, 12, 5, 2, 10, 0, NA, 0, 1)
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+MUX_CFG("R13_1710_USB1_SEO", A, 12, 5, 2, 10, 0, NA, 0, 1)
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+
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+/* USB2 master */
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+MUX_CFG("USB2_SUSP", B, 3, 1, 2, 17, 0, NA, 0, 1)
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+MUX_CFG("USB2_VP", B, 6, 1, 2, 18, 0, NA, 0, 1)
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+MUX_CFG("USB2_TXEN", B, 9, 1, 2, 19, 0, NA, 0, 1)
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+MUX_CFG("USB2_VM", C, 18, 1, 3, 0, 0, NA, 0, 1)
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+MUX_CFG("USB2_RCV", C, 21, 1, 3, 1, 0, NA, 0, 1)
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+MUX_CFG("USB2_SE0", C, 24, 2, 3, 2, 0, NA, 0, 1)
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+MUX_CFG("USB2_TXD", C, 27, 2, 3, 3, 0, NA, 0, 1)
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+
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+/* OMAP-1510 GPIO */
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+MUX_CFG("R18_1510_GPIO0", 7, 9, 0, 1, 11, 1, 0, 0, 1)
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+MUX_CFG("R19_1510_GPIO1", 7, 6, 0, 1, 10, 1, 0, 0, 1)
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+MUX_CFG("M14_1510_GPIO2", 7, 3, 0, 1, 9, 1, 0, 0, 1)
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+
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+/* OMAP1610 GPIO */
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+MUX_CFG("P18_1610_GPIO3", 7, 0, 0, 1, 8, 0, NA, 0, 1)
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+MUX_CFG("Y15_1610_GPIO17", A, 0, 7, 2, 6, 0, NA, 0, 1)
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+
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+/* OMAP-1710 GPIO */
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+MUX_CFG("R18_1710_GPIO0", 7, 9, 0, 1, 11, 1, 1, 1, 1)
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+MUX_CFG("V2_1710_GPIO10", F, 27, 1, 4, 3, 1, 4, 1, 1)
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+MUX_CFG("N21_1710_GPIO14", 6, 9, 0, 1, 1, 1, 1, 1, 1)
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+MUX_CFG("W15_1710_GPIO40", 9, 27, 7, 2, 5, 1, 2, 1, 1)
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+
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+/* MPUIO */
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+MUX_CFG("MPUIO2", 7, 18, 0, 1, 14, 1, NA, 0, 1)
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+MUX_CFG("N15_1610_MPUIO2", 7, 18, 0, 1, 14, 1, 1, 0, 1)
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+MUX_CFG("MPUIO4", 7, 15, 0, 1, 13, 1, NA, 0, 1)
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+MUX_CFG("MPUIO5", 7, 12, 0, 1, 12, 1, NA, 0, 1)
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+
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+MUX_CFG("T20_1610_MPUIO5", 7, 12, 0, 1, 12, 0, 3, 0, 1)
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+MUX_CFG("W11_1610_MPUIO6", 10, 15, 2, 3, 8, 0, 3, 0, 1)
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+MUX_CFG("V10_1610_MPUIO7", A, 24, 2, 2, 14, 0, 2, 0, 1)
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+MUX_CFG("W11_1610_MPUIO9", 10, 15, 1, 3, 8, 0, 3, 0, 1)
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+MUX_CFG("V10_1610_MPUIO10", A, 24, 1, 2, 14, 0, 2, 0, 1)
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+MUX_CFG("W10_1610_MPUIO11", A, 18, 2, 2, 11, 0, 2, 0, 1)
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+MUX_CFG("E20_1610_MPUIO13", 3, 21, 1, 0, 7, 0, 0, 0, 1)
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+MUX_CFG("U20_1610_MPUIO14", 9, 6, 6, 0, 30, 0, 0, 0, 1)
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+MUX_CFG("E19_1610_MPUIO15", 3, 18, 1, 0, 6, 0, 0, 0, 1)
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+
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+/* MCBSP2 */
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+MUX_CFG("MCBSP2_CLKR", C, 6, 0, 2, 27, 1, NA, 0, 1)
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+MUX_CFG("MCBSP2_CLKX", C, 9, 0, 2, 29, 1, NA, 0, 1)
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+MUX_CFG("MCBSP2_DR", C, 0, 0, 2, 26, 1, NA, 0, 1)
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+MUX_CFG("MCBSP2_DX", C, 15, 0, 2, 31, 1, NA, 0, 1)
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+MUX_CFG("MCBSP2_FSR", C, 12, 0, 2, 30, 1, NA, 0, 1)
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+MUX_CFG("MCBSP2_FSX", C, 3, 0, 2, 27, 1, NA, 0, 1)
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+
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+/* MCBSP3 NOTE: Mode must 1 for clock */
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+MUX_CFG("MCBSP3_CLKX", 9, 3, 1, 1, 29, 0, NA, 0, 1)
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+
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+/* Misc ballouts */
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+MUX_CFG("BALLOUT_V8_ARMIO3", B, 18, 0, 2, 25, 1, NA, 0, 1)
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+MUX_CFG("N20_HDQ", 6, 18, 1, 1, 4, 0, 1, 4, 0)
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+
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+/* OMAP-1610 MMC2 */
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+MUX_CFG("W8_1610_MMC2_DAT0", B, 21, 6, 2, 23, 1, 2, 1, 1)
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+MUX_CFG("V8_1610_MMC2_DAT1", B, 27, 6, 2, 25, 1, 2, 1, 1)
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+MUX_CFG("W15_1610_MMC2_DAT2", 9, 12, 6, 2, 5, 1, 2, 1, 1)
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+MUX_CFG("R10_1610_MMC2_DAT3", B, 18, 6, 2, 22, 1, 2, 1, 1)
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+MUX_CFG("Y10_1610_MMC2_CLK", B, 3, 6, 2, 17, 0, 2, 0, 1)
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+MUX_CFG("Y8_1610_MMC2_CMD", B, 24, 6, 2, 24, 1, 2, 1, 1)
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+MUX_CFG("V9_1610_MMC2_CMDDIR", B, 12, 6, 2, 20, 0, 2, 1, 1)
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+MUX_CFG("V5_1610_MMC2_DATDIR0", B, 15, 6, 2, 21, 0, 2, 1, 1)
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+MUX_CFG("W19_1610_MMC2_DATDIR1", 8, 15, 6, 1, 23, 0, 1, 1, 1)
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+MUX_CFG("R18_1610_MMC2_CLKIN", 7, 9, 6, 1, 11, 0, 1, 11, 1)
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+
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+/* OMAP-1610 External Trace Interface */
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+MUX_CFG("M19_1610_ETM_PSTAT0", 5, 27, 1, 0, 29, 0, 0, 0, 1)
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+MUX_CFG("L15_1610_ETM_PSTAT1", 5, 24, 1, 0, 28, 0, 0, 0, 1)
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徐寅秋