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@@ -133,3 +133,160 @@
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#define OMAP3430_GRPSEL_GPIO2_MASK (1 << 13)
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#define OMAP3430_GRPSEL_UART3_MASK (1 << 11)
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#define OMAP3430_GRPSEL_GPT9_MASK (1 << 10)
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+#define OMAP3430_GRPSEL_GPT8_MASK (1 << 9)
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+#define OMAP3430_GRPSEL_GPT7_MASK (1 << 8)
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+#define OMAP3430_GRPSEL_GPT6_MASK (1 << 7)
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+#define OMAP3430_GRPSEL_GPT5_MASK (1 << 6)
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+#define OMAP3430_GRPSEL_GPT4_MASK (1 << 5)
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+#define OMAP3430_GRPSEL_GPT3_MASK (1 << 4)
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+#define OMAP3430_GRPSEL_GPT2_MASK (1 << 3)
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+#define OMAP3430_GRPSEL_MCBSP4_MASK (1 << 2)
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+#define OMAP3430_GRPSEL_MCBSP3_MASK (1 << 1)
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+#define OMAP3430_GRPSEL_MCBSP2_MASK (1 << 0)
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+
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+/* PM_MPUGRPSEL_WKUP, PM_IVA2GRPSEL_WKUP shared bits */
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+#define OMAP3430_GRPSEL_IO_MASK (1 << 8)
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+#define OMAP3430_GRPSEL_SR2_MASK (1 << 7)
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+#define OMAP3430_GRPSEL_SR1_MASK (1 << 6)
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+#define OMAP3430_GRPSEL_GPIO1_MASK (1 << 3)
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+#define OMAP3430_GRPSEL_GPT12_MASK (1 << 1)
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+#define OMAP3430_GRPSEL_GPT1_MASK (1 << 0)
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+
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+/* Bits specific to each register */
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+
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+/* RM_RSTCTRL_IVA2 */
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+#define OMAP3430_RST3_IVA2_MASK (1 << 2)
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+#define OMAP3430_RST2_IVA2_MASK (1 << 1)
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+#define OMAP3430_RST1_IVA2_MASK (1 << 0)
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+
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+/* RM_RSTST_IVA2 specific bits */
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+#define OMAP3430_EMULATION_VSEQ_RST_MASK (1 << 13)
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+#define OMAP3430_EMULATION_VHWA_RST_MASK (1 << 12)
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+#define OMAP3430_EMULATION_IVA2_RST_MASK (1 << 11)
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+#define OMAP3430_IVA2_SW_RST3_MASK (1 << 10)
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+#define OMAP3430_IVA2_SW_RST2_MASK (1 << 9)
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+#define OMAP3430_IVA2_SW_RST1_MASK (1 << 8)
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+
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+/* PM_WKDEP_IVA2 specific bits */
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+
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+/* PM_PWSTCTRL_IVA2 specific bits */
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+#define OMAP3430_L2FLATMEMONSTATE_SHIFT 22
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+#define OMAP3430_L2FLATMEMONSTATE_MASK (0x3 << 22)
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+#define OMAP3430_SHAREDL2CACHEFLATONSTATE_SHIFT 20
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+#define OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK (0x3 << 20)
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+#define OMAP3430_L1FLATMEMONSTATE_SHIFT 18
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+#define OMAP3430_L1FLATMEMONSTATE_MASK (0x3 << 18)
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+#define OMAP3430_SHAREDL1CACHEFLATONSTATE_SHIFT 16
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+#define OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK (0x3 << 16)
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+#define OMAP3430_L2FLATMEMRETSTATE_MASK (1 << 11)
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+#define OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK (1 << 10)
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+#define OMAP3430_L1FLATMEMRETSTATE_MASK (1 << 9)
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+#define OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK (1 << 8)
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+
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+/* PM_PWSTST_IVA2 specific bits */
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+#define OMAP3430_L2FLATMEMSTATEST_SHIFT 10
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+#define OMAP3430_L2FLATMEMSTATEST_MASK (0x3 << 10)
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+#define OMAP3430_SHAREDL2CACHEFLATSTATEST_SHIFT 8
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+#define OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK (0x3 << 8)
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+#define OMAP3430_L1FLATMEMSTATEST_SHIFT 6
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+#define OMAP3430_L1FLATMEMSTATEST_MASK (0x3 << 6)
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+#define OMAP3430_SHAREDL1CACHEFLATSTATEST_SHIFT 4
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+#define OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK (0x3 << 4)
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+
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+/* PM_PREPWSTST_IVA2 specific bits */
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+#define OMAP3430_LASTL2FLATMEMSTATEENTERED_SHIFT 10
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+#define OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK (0x3 << 10)
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+#define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_SHIFT 8
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+#define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK (0x3 << 8)
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+#define OMAP3430_LASTL1FLATMEMSTATEENTERED_SHIFT 6
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+#define OMAP3430_LASTL1FLATMEMSTATEENTERED_MASK (0x3 << 6)
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+#define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_SHIFT 4
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+#define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_MASK (0x3 << 4)
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+
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+/* PRM_IRQSTATUS_IVA2 specific bits */
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+#define OMAP3430_PRM_IRQSTATUS_IVA2_IVA2_DPLL_ST_MASK (1 << 2)
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+#define OMAP3430_FORCEWKUP_ST_MASK (1 << 1)
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+
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+/* PRM_IRQENABLE_IVA2 specific bits */
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+#define OMAP3430_PRM_IRQENABLE_IVA2_IVA2_DPLL_RECAL_EN_MASK (1 << 2)
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+#define OMAP3430_FORCEWKUP_EN_MASK (1 << 1)
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+
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+/* PRM_REVISION specific bits */
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+
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+/* PRM_SYSCONFIG specific bits */
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+
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+/* PRM_IRQSTATUS_MPU specific bits */
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+#define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT 25
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+#define OMAP3430ES2_SND_PERIPH_DPLL_ST_MASK (1 << 25)
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+#define OMAP3430_VC_TIMEOUTERR_ST_MASK (1 << 24)
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+#define OMAP3430_VC_RAERR_ST_MASK (1 << 23)
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+#define OMAP3430_VC_SAERR_ST_MASK (1 << 22)
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+#define OMAP3430_VP2_TRANXDONE_ST_MASK (1 << 21)
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+#define OMAP3430_VP2_EQVALUE_ST_MASK (1 << 20)
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+#define OMAP3430_VP2_NOSMPSACK_ST_MASK (1 << 19)
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+#define OMAP3430_VP2_MAXVDD_ST_MASK (1 << 18)
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+#define OMAP3430_VP2_MINVDD_ST_MASK (1 << 17)
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+#define OMAP3430_VP2_OPPCHANGEDONE_ST_MASK (1 << 16)
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+#define OMAP3430_VP1_TRANXDONE_ST_MASK (1 << 15)
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+#define OMAP3430_VP1_EQVALUE_ST_MASK (1 << 14)
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+#define OMAP3430_VP1_NOSMPSACK_ST_MASK (1 << 13)
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+#define OMAP3430_VP1_MAXVDD_ST_MASK (1 << 12)
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+#define OMAP3430_VP1_MINVDD_ST_MASK (1 << 11)
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+#define OMAP3430_VP1_OPPCHANGEDONE_ST_MASK (1 << 10)
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+#define OMAP3430_IO_ST_MASK (1 << 9)
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+#define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_MASK (1 << 8)
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+#define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT 8
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+#define OMAP3430_MPU_DPLL_ST_MASK (1 << 7)
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+#define OMAP3430_MPU_DPLL_ST_SHIFT 7
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+#define OMAP3430_PERIPH_DPLL_ST_MASK (1 << 6)
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+#define OMAP3430_PERIPH_DPLL_ST_SHIFT 6
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+#define OMAP3430_CORE_DPLL_ST_MASK (1 << 5)
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+#define OMAP3430_CORE_DPLL_ST_SHIFT 5
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+#define OMAP3430_TRANSITION_ST_MASK (1 << 4)
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+#define OMAP3430_EVGENOFF_ST_MASK (1 << 3)
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+#define OMAP3430_EVGENON_ST_MASK (1 << 2)
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+#define OMAP3430_FS_USB_WKUP_ST_MASK (1 << 1)
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+
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+/* PRM_IRQENABLE_MPU specific bits */
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+#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT 25
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+#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_MASK (1 << 25)
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+#define OMAP3430_VC_TIMEOUTERR_EN_MASK (1 << 24)
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+#define OMAP3430_VC_RAERR_EN_MASK (1 << 23)
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+#define OMAP3430_VC_SAERR_EN_MASK (1 << 22)
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+#define OMAP3430_VP2_TRANXDONE_EN_MASK (1 << 21)
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+#define OMAP3430_VP2_EQVALUE_EN_MASK (1 << 20)
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+#define OMAP3430_VP2_NOSMPSACK_EN_MASK (1 << 19)
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+#define OMAP3430_VP2_MAXVDD_EN_MASK (1 << 18)
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+#define OMAP3430_VP2_MINVDD_EN_MASK (1 << 17)
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+#define OMAP3430_VP2_OPPCHANGEDONE_EN_MASK (1 << 16)
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+#define OMAP3430_VP1_TRANXDONE_EN_MASK (1 << 15)
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+#define OMAP3430_VP1_EQVALUE_EN_MASK (1 << 14)
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+#define OMAP3430_VP1_NOSMPSACK_EN_MASK (1 << 13)
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+#define OMAP3430_VP1_MAXVDD_EN_MASK (1 << 12)
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+#define OMAP3430_VP1_MINVDD_EN_MASK (1 << 11)
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+#define OMAP3430_VP1_OPPCHANGEDONE_EN_MASK (1 << 10)
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+#define OMAP3430_IO_EN_MASK (1 << 9)
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+#define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_MASK (1 << 8)
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+#define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT 8
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+#define OMAP3430_MPU_DPLL_RECAL_EN_MASK (1 << 7)
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+#define OMAP3430_MPU_DPLL_RECAL_EN_SHIFT 7
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+#define OMAP3430_PERIPH_DPLL_RECAL_EN_MASK (1 << 6)
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+#define OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT 6
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+#define OMAP3430_CORE_DPLL_RECAL_EN_MASK (1 << 5)
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+#define OMAP3430_CORE_DPLL_RECAL_EN_SHIFT 5
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+#define OMAP3430_TRANSITION_EN_MASK (1 << 4)
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+#define OMAP3430_EVGENOFF_EN_MASK (1 << 3)
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+#define OMAP3430_EVGENON_EN_MASK (1 << 2)
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+#define OMAP3430_FS_USB_WKUP_EN_MASK (1 << 1)
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+
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+/* RM_RSTST_MPU specific bits */
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+#define OMAP3430_EMULATION_MPU_RST_MASK (1 << 11)
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+
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+/* PM_WKDEP_MPU specific bits */
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+#define OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT 5
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+#define OMAP3430_PM_WKDEP_MPU_EN_DSS_MASK (1 << 5)
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+#define OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT 2
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+#define OMAP3430_PM_WKDEP_MPU_EN_IVA2_MASK (1 << 2)
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+
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+/* PM_EVGENCTRL_MPU */
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+#define OMAP3430_OFFLOADMODE_SHIFT 3
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