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@@ -584,3 +584,145 @@ struct bfin_can_regs {
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#define MBTIF31 0x8000 /* TX Interrupt Active In Mailbox 31 */
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#define MBTIF31 0x8000 /* TX Interrupt Active In Mailbox 31 */
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/* CAN_MBRIF1 Masks */
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/* CAN_MBRIF1 Masks */
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+#define MBRIF0 0x0001 /* RX Interrupt Active In Mailbox 0 */
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+#define MBRIF1 0x0002 /* RX Interrupt Active In Mailbox 1 */
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+#define MBRIF2 0x0004 /* RX Interrupt Active In Mailbox 2 */
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+#define MBRIF3 0x0008 /* RX Interrupt Active In Mailbox 3 */
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+#define MBRIF4 0x0010 /* RX Interrupt Active In Mailbox 4 */
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+#define MBRIF5 0x0020 /* RX Interrupt Active In Mailbox 5 */
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+#define MBRIF6 0x0040 /* RX Interrupt Active In Mailbox 6 */
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+#define MBRIF7 0x0080 /* RX Interrupt Active In Mailbox 7 */
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+#define MBRIF8 0x0100 /* RX Interrupt Active In Mailbox 8 */
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+#define MBRIF9 0x0200 /* RX Interrupt Active In Mailbox 9 */
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+#define MBRIF10 0x0400 /* RX Interrupt Active In Mailbox 10 */
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+#define MBRIF11 0x0800 /* RX Interrupt Active In Mailbox 11 */
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+#define MBRIF12 0x1000 /* RX Interrupt Active In Mailbox 12 */
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+#define MBRIF13 0x2000 /* RX Interrupt Active In Mailbox 13 */
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+#define MBRIF14 0x4000 /* RX Interrupt Active In Mailbox 14 */
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+#define MBRIF15 0x8000 /* RX Interrupt Active In Mailbox 15 */
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+
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+/* CAN_MBRIF2 Masks */
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+#define MBRIF16 0x0001 /* RX Interrupt Active In Mailbox 16 */
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+#define MBRIF17 0x0002 /* RX Interrupt Active In Mailbox 17 */
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+#define MBRIF18 0x0004 /* RX Interrupt Active In Mailbox 18 */
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+#define MBRIF19 0x0008 /* RX Interrupt Active In Mailbox 19 */
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+#define MBRIF20 0x0010 /* RX Interrupt Active In Mailbox 20 */
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+#define MBRIF21 0x0020 /* RX Interrupt Active In Mailbox 21 */
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+#define MBRIF22 0x0040 /* RX Interrupt Active In Mailbox 22 */
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+#define MBRIF23 0x0080 /* RX Interrupt Active In Mailbox 23 */
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+#define MBRIF24 0x0100 /* RX Interrupt Active In Mailbox 24 */
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+#define MBRIF25 0x0200 /* RX Interrupt Active In Mailbox 25 */
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+#define MBRIF26 0x0400 /* RX Interrupt Active In Mailbox 26 */
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+#define MBRIF27 0x0800 /* RX Interrupt Active In Mailbox 27 */
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+#define MBRIF28 0x1000 /* RX Interrupt Active In Mailbox 28 */
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+#define MBRIF29 0x2000 /* RX Interrupt Active In Mailbox 29 */
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+#define MBRIF30 0x4000 /* RX Interrupt Active In Mailbox 30 */
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+#define MBRIF31 0x8000 /* RX Interrupt Active In Mailbox 31 */
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+
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+/* CAN_MBIM1 Masks */
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+#define MBIM0 0x0001 /* Enable Interrupt For Mailbox 0 */
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+#define MBIM1 0x0002 /* Enable Interrupt For Mailbox 1 */
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+#define MBIM2 0x0004 /* Enable Interrupt For Mailbox 2 */
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+#define MBIM3 0x0008 /* Enable Interrupt For Mailbox 3 */
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+#define MBIM4 0x0010 /* Enable Interrupt For Mailbox 4 */
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+#define MBIM5 0x0020 /* Enable Interrupt For Mailbox 5 */
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+#define MBIM6 0x0040 /* Enable Interrupt For Mailbox 6 */
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+#define MBIM7 0x0080 /* Enable Interrupt For Mailbox 7 */
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+#define MBIM8 0x0100 /* Enable Interrupt For Mailbox 8 */
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+#define MBIM9 0x0200 /* Enable Interrupt For Mailbox 9 */
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+#define MBIM10 0x0400 /* Enable Interrupt For Mailbox 10 */
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+#define MBIM11 0x0800 /* Enable Interrupt For Mailbox 11 */
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+#define MBIM12 0x1000 /* Enable Interrupt For Mailbox 12 */
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+#define MBIM13 0x2000 /* Enable Interrupt For Mailbox 13 */
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+#define MBIM14 0x4000 /* Enable Interrupt For Mailbox 14 */
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+#define MBIM15 0x8000 /* Enable Interrupt For Mailbox 15 */
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+
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+/* CAN_MBIM2 Masks */
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+#define MBIM16 0x0001 /* Enable Interrupt For Mailbox 16 */
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+#define MBIM17 0x0002 /* Enable Interrupt For Mailbox 17 */
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+#define MBIM18 0x0004 /* Enable Interrupt For Mailbox 18 */
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+#define MBIM19 0x0008 /* Enable Interrupt For Mailbox 19 */
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+#define MBIM20 0x0010 /* Enable Interrupt For Mailbox 20 */
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+#define MBIM21 0x0020 /* Enable Interrupt For Mailbox 21 */
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+#define MBIM22 0x0040 /* Enable Interrupt For Mailbox 22 */
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+#define MBIM23 0x0080 /* Enable Interrupt For Mailbox 23 */
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+#define MBIM24 0x0100 /* Enable Interrupt For Mailbox 24 */
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+#define MBIM25 0x0200 /* Enable Interrupt For Mailbox 25 */
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+#define MBIM26 0x0400 /* Enable Interrupt For Mailbox 26 */
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+#define MBIM27 0x0800 /* Enable Interrupt For Mailbox 27 */
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+#define MBIM28 0x1000 /* Enable Interrupt For Mailbox 28 */
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+#define MBIM29 0x2000 /* Enable Interrupt For Mailbox 29 */
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+#define MBIM30 0x4000 /* Enable Interrupt For Mailbox 30 */
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+#define MBIM31 0x8000 /* Enable Interrupt For Mailbox 31 */
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+
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+/* CAN_GIM Masks */
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+#define EWTIM 0x0001 /* Enable TX Error Count Interrupt */
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+#define EWRIM 0x0002 /* Enable RX Error Count Interrupt */
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+#define EPIM 0x0004 /* Enable Error-Passive Mode Interrupt */
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+#define BOIM 0x0008 /* Enable Bus Off Interrupt */
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+#define WUIM 0x0010 /* Enable Wake-Up Interrupt */
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+#define UIAIM 0x0020 /* Enable Access To Unimplemented Address Interrupt */
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+#define AAIM 0x0040 /* Enable Abort Acknowledge Interrupt */
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+#define RMLIM 0x0080 /* Enable RX Message Lost Interrupt */
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+#define UCEIM 0x0100 /* Enable Universal Counter Overflow Interrupt */
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+#define EXTIM 0x0200 /* Enable External Trigger Output Interrupt */
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+#define ADIM 0x0400 /* Enable Access Denied Interrupt */
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+
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+/* CAN_GIS Masks */
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+#define EWTIS 0x0001 /* TX Error Count IRQ Status */
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+#define EWRIS 0x0002 /* RX Error Count IRQ Status */
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+#define EPIS 0x0004 /* Error-Passive Mode IRQ Status */
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+#define BOIS 0x0008 /* Bus Off IRQ Status */
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+#define WUIS 0x0010 /* Wake-Up IRQ Status */
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+#define UIAIS 0x0020 /* Access To Unimplemented Address IRQ Status */
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+#define AAIS 0x0040 /* Abort Acknowledge IRQ Status */
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+#define RMLIS 0x0080 /* RX Message Lost IRQ Status */
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+#define UCEIS 0x0100 /* Universal Counter Overflow IRQ Status */
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+#define EXTIS 0x0200 /* External Trigger Output IRQ Status */
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+#define ADIS 0x0400 /* Access Denied IRQ Status */
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+
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+/* CAN_GIF Masks */
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+#define EWTIF 0x0001 /* TX Error Count IRQ Flag */
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+#define EWRIF 0x0002 /* RX Error Count IRQ Flag */
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+#define EPIF 0x0004 /* Error-Passive Mode IRQ Flag */
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+#define BOIF 0x0008 /* Bus Off IRQ Flag */
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+#define WUIF 0x0010 /* Wake-Up IRQ Flag */
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+#define UIAIF 0x0020 /* Access To Unimplemented Address IRQ Flag */
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+#define AAIF 0x0040 /* Abort Acknowledge IRQ Flag */
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+#define RMLIF 0x0080 /* RX Message Lost IRQ Flag */
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+#define UCEIF 0x0100 /* Universal Counter Overflow IRQ Flag */
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+#define EXTIF 0x0200 /* External Trigger Output IRQ Flag */
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+#define ADIF 0x0400 /* Access Denied IRQ Flag */
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+
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+/* CAN_UCCNF Masks */
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+#define UCCNF 0x000F /* Universal Counter Mode */
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+#define UC_STAMP 0x0001 /* Timestamp Mode */
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+#define UC_WDOG 0x0002 /* Watchdog Mode */
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+#define UC_AUTOTX 0x0003 /* Auto-Transmit Mode */
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+#define UC_ERROR 0x0006 /* CAN Error Frame Count */
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+#define UC_OVER 0x0007 /* CAN Overload Frame Count */
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+#define UC_LOST 0x0008 /* Arbitration Lost During TX Count */
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+#define UC_AA 0x0009 /* TX Abort Count */
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+#define UC_TA 0x000A /* TX Successful Count */
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+#define UC_REJECT 0x000B /* RX Message Rejected Count */
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+#define UC_RML 0x000C /* RX Message Lost Count */
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+#define UC_RX 0x000D /* Total Successful RX Messages Count */
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+#define UC_RMP 0x000E /* Successful RX W/Matching ID Count */
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+#define UC_ALL 0x000F /* Correct Message On CAN Bus Line Count */
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+#define UCRC 0x0020 /* Universal Counter Reload/Clear */
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+#define UCCT 0x0040 /* Universal Counter CAN Trigger */
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+#define UCE 0x0080 /* Universal Counter Enable */
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+
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+/* CAN_ESR Masks */
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+#define ACKE 0x0004 /* Acknowledge Error */
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+#define SER 0x0008 /* Stuff Error */
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+#define CRCE 0x0010 /* CRC Error */
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+#define SA0 0x0020 /* Stuck At Dominant Error */
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+#define BEF 0x0040 /* Bit Error Flag */
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+#define FER 0x0080 /* Form Error Flag */
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+
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+/* CAN_EWR Masks */
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+#define EWLREC 0x00FF /* RX Error Count Limit (For EWRIS) */
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+#define EWLTEC 0xFF00 /* TX Error Count Limit (For EWTIS) */
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+
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+#endif
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