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@@ -845,3 +845,190 @@
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#define CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */
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#define CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */
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+#define CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */
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+#define CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */
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+#define CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */
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+#define CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */
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+#define CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */
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+#define CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */
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+#define CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */
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+
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+#define CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */
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+#define CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */
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+#define CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */
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+#define CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */
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+#define CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */
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+#define CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */
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+#define CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */
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+#define CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */
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+
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+#define CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */
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+#define CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */
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+#define CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */
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+#define CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */
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+#define CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */
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+#define CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */
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+#define CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */
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+#define CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */
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+
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+#define CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */
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+#define CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */
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+#define CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */
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+#define CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */
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+#define CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */
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+#define CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */
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+#define CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */
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+#define CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */
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+
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+#define CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */
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+#define CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */
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+#define CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */
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+#define CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */
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+#define CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */
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+#define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */
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+#define CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */
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+#define CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */
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+
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+#define CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */
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+#define CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */
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+#define CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */
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+#define CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */
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+#define CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */
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+#define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */
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+#define CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */
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+#define CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */
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+
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+#define CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */
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+#define CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */
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+#define CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */
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+#define CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */
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+#define CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */
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+#define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */
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+#define CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */
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+#define CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */
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+
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+/* CAN Mailbox Area Macros */
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+#define CAN_MB_ID1(x) (CAN_MB00_ID1+((x)*0x20))
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+#define CAN_MB_ID0(x) (CAN_MB00_ID0+((x)*0x20))
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+#define CAN_MB_TIMESTAMP(x) (CAN_MB00_TIMESTAMP+((x)*0x20))
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+#define CAN_MB_LENGTH(x) (CAN_MB00_LENGTH+((x)*0x20))
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+#define CAN_MB_DATA3(x) (CAN_MB00_DATA3+((x)*0x20))
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+#define CAN_MB_DATA2(x) (CAN_MB00_DATA2+((x)*0x20))
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+#define CAN_MB_DATA1(x) (CAN_MB00_DATA1+((x)*0x20))
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+#define CAN_MB_DATA0(x) (CAN_MB00_DATA0+((x)*0x20))
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+
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+/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
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+#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
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+#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
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+#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
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+#define BFIN_PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */
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+
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+/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
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+#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
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+#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
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+#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
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+#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshold Register */
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+#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
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+#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
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+#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
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+
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+#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
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+#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
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+#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
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+#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshold Register */
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+#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
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+#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
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+#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
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+
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+/***********************************************************************************
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+** System MMR Register Bits And Macros
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+**
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+** Disclaimer: All macros are intended to make C and Assembly code more readable.
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+** Use these macros carefully, as any that do left shifts for field
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+** depositing will result in the lower order bits being destroyed. Any
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+** macro that shifts left to properly position the bit-field should be
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+** used as part of an OR to initialize a register and NOT as a dynamic
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+** modifier UNLESS the lower order bits are saved and ORed back in when
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+** the macro is used.
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+*************************************************************************************/
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+
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+/* CHIPID Masks */
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+#define CHIPID_VERSION 0xF0000000
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+#define CHIPID_FAMILY 0x0FFFF000
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+#define CHIPID_MANUFACTURE 0x00000FFE
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+
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+/* SWRST Masks */
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+#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
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+#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
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+#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
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+#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
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+#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
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+
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+/* SYSCR Masks */
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+#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */
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+#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
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+
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+/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
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+
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+/* SIC_IAR0 Macros */
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+#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
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+#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
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+#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
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+#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */
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+#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
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+#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
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+#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
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+#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
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+
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+/* SIC_IAR1 Macros */
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+#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */
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+#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
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+#define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
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+#define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */
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+#define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
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+#define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
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+#define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
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+#define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
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+
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+/* SIC_IAR2 Macros */
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+#define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */
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+#define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
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+#define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
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+#define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */
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+#define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
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+#define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
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+#define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
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+#define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
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+
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+/* SIC_IAR3 Macros */
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+#define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */
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+#define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */
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+#define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */
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+#define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */
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+#define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */
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+#define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */
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+#define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */
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+#define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */
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+
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+/* SIC_IMASK Masks */
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+#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
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+#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
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+#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
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+#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
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+
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+/* SIC_IWR Masks */
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+#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
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+#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
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+#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
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+#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
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+
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+/* **************** GENERAL PURPOSE TIMER MASKS **********************/
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+/* TIMER_ENABLE Masks */
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+#define TIMEN0 0x0001 /* Enable Timer 0 */
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+#define TIMEN1 0x0002 /* Enable Timer 1 */
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+#define TIMEN2 0x0004 /* Enable Timer 2 */
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+#define TIMEN3 0x0008 /* Enable Timer 3 */
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+#define TIMEN4 0x0010 /* Enable Timer 4 */
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+#define TIMEN5 0x0020 /* Enable Timer 5 */
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+#define TIMEN6 0x0040 /* Enable Timer 6 */
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+#define TIMEN7 0x0080 /* Enable Timer 7 */
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李欣儒