|
|
@@ -490,3 +490,98 @@ static struct clk dpll4_m2x2_ck_3630 = {
|
|
|
.parent_names = dpll4_m2x2_ck_parent_names,
|
|
|
.num_parents = ARRAY_SIZE(dpll4_m2x2_ck_parent_names),
|
|
|
.ops = &dpll4_m5x2_ck_3630_ops,
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk omap_96m_alwon_fck;
|
|
|
+
|
|
|
+static const char *omap_96m_alwon_fck_parent_names[] = {
|
|
|
+ "dpll4_m2x2_ck",
|
|
|
+};
|
|
|
+
|
|
|
+DEFINE_STRUCT_CLK_HW_OMAP(omap_96m_alwon_fck, NULL);
|
|
|
+DEFINE_STRUCT_CLK(omap_96m_alwon_fck, omap_96m_alwon_fck_parent_names,
|
|
|
+ core_ck_ops);
|
|
|
+
|
|
|
+static struct clk cm_96m_fck;
|
|
|
+
|
|
|
+static const char *cm_96m_fck_parent_names[] = {
|
|
|
+ "omap_96m_alwon_fck",
|
|
|
+};
|
|
|
+
|
|
|
+DEFINE_STRUCT_CLK_HW_OMAP(cm_96m_fck, NULL);
|
|
|
+DEFINE_STRUCT_CLK(cm_96m_fck, cm_96m_fck_parent_names, core_ck_ops);
|
|
|
+
|
|
|
+static const struct clksel_rate clkout2_src_54m_rates[] = {
|
|
|
+ { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
|
|
|
+ { .div = 0 }
|
|
|
+};
|
|
|
+
|
|
|
+DEFINE_CLK_DIVIDER(dpll4_m3_ck, "dpll4_ck", &dpll4_ck, 0x0,
|
|
|
+ OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
|
|
|
+ OMAP3430_CLKSEL_TV_SHIFT, OMAP3630_CLKSEL_TV_WIDTH,
|
|
|
+ CLK_DIVIDER_ONE_BASED, NULL);
|
|
|
+
|
|
|
+static struct clk dpll4_m3x2_ck;
|
|
|
+
|
|
|
+static const char *dpll4_m3x2_ck_parent_names[] = {
|
|
|
+ "dpll4_m3_ck",
|
|
|
+};
|
|
|
+
|
|
|
+static struct clk_hw_omap dpll4_m3x2_ck_hw = {
|
|
|
+ .hw = {
|
|
|
+ .clk = &dpll4_m3x2_ck,
|
|
|
+ },
|
|
|
+ .ops = &clkhwops_wait,
|
|
|
+ .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
|
|
|
+ .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
|
|
|
+ .flags = INVERT_ENABLE,
|
|
|
+ .clkdm_name = "dpll4_clkdm",
|
|
|
+};
|
|
|
+
|
|
|
+DEFINE_STRUCT_CLK(dpll4_m3x2_ck, dpll4_m3x2_ck_parent_names, dpll4_m5x2_ck_ops);
|
|
|
+
|
|
|
+static struct clk dpll4_m3x2_ck_3630 = {
|
|
|
+ .name = "dpll4_m3x2_ck",
|
|
|
+ .hw = &dpll4_m3x2_ck_hw.hw,
|
|
|
+ .parent_names = dpll4_m3x2_ck_parent_names,
|
|
|
+ .num_parents = ARRAY_SIZE(dpll4_m3x2_ck_parent_names),
|
|
|
+ .ops = &dpll4_m5x2_ck_3630_ops,
|
|
|
+};
|
|
|
+
|
|
|
+static const char *omap_54m_fck_parent_names[] = {
|
|
|
+ "dpll4_m3x2_ck", "sys_altclk",
|
|
|
+};
|
|
|
+
|
|
|
+DEFINE_CLK_MUX(omap_54m_fck, omap_54m_fck_parent_names, NULL, 0x0,
|
|
|
+ OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP3430_SOURCE_54M_SHIFT,
|
|
|
+ OMAP3430_SOURCE_54M_WIDTH, 0x0, NULL);
|
|
|
+
|
|
|
+static const struct clksel clkout2_src_clksel[] = {
|
|
|
+ { .parent = &core_ck, .rates = clkout2_src_core_rates },
|
|
|
+ { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
|
|
|
+ { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates },
|
|
|
+ { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
|
|
|
+ { .parent = NULL },
|
|
|
+};
|
|
|
+
|
|
|
+static const char *clkout2_src_ck_parent_names[] = {
|
|
|
+ "core_ck", "sys_ck", "cm_96m_fck", "omap_54m_fck",
|
|
|
+};
|
|
|
+
|
|
|
+static const struct clk_ops clkout2_src_ck_ops = {
|
|
|
+ .init = &omap2_init_clk_clkdm,
|
|
|
+ .enable = &omap2_dflt_clk_enable,
|
|
|
+ .disable = &omap2_dflt_clk_disable,
|
|
|
+ .is_enabled = &omap2_dflt_clk_is_enabled,
|
|
|
+ .recalc_rate = &omap2_clksel_recalc,
|
|
|
+ .get_parent = &omap2_clksel_find_parent_index,
|
|
|
+ .set_parent = &omap2_clksel_set_parent,
|
|
|
+};
|
|
|
+
|
|
|
+DEFINE_CLK_OMAP_MUX_GATE(clkout2_src_ck, "core_clkdm",
|
|
|
+ clkout2_src_clksel, OMAP3430_CM_CLKOUT_CTRL,
|
|
|
+ OMAP3430_CLKOUT2SOURCE_MASK,
|
|
|
+ OMAP3430_CM_CLKOUT_CTRL, OMAP3430_CLKOUT2_EN_SHIFT,
|
|
|
+ NULL, clkout2_src_ck_parent_names, clkout2_src_ck_ops);
|
|
|
+
|
|
|
+static const struct clksel_rate omap_48m_cm96m_rates[] = {
|
韩正义