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@@ -285,3 +285,87 @@ void __init omap4xxx_check_features(void)
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void __init ti81xx_check_features(void)
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void __init ti81xx_check_features(void)
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{
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{
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+ omap_features = OMAP3_HAS_NEON;
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+ omap3_cpuinfo();
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+}
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+
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+void __init omap3xxx_check_revision(void)
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+{
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+ u32 cpuid, idcode;
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+ u16 hawkeye;
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+ u8 rev;
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+
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+ /*
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+ * We cannot access revision registers on ES1.0.
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+ * If the processor type is Cortex-A8 and the revision is 0x0
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+ * it means its Cortex r0p0 which is 3430 ES1.0.
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+ */
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+ cpuid = read_cpuid(CPUID_ID);
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+ if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
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+ omap_revision = OMAP3430_REV_ES1_0;
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+ cpu_rev = "1.0";
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+ return;
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+ }
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+
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+ /*
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+ * Detection for 34xx ES2.0 and above can be done with just
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+ * hawkeye and rev. See TRM 1.5.2 Device Identification.
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+ * Note that rev does not map directly to our defined processor
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+ * revision numbers as ES1.0 uses value 0.
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+ */
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+ idcode = read_tap_reg(OMAP_TAP_IDCODE);
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+ hawkeye = (idcode >> 12) & 0xffff;
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+ rev = (idcode >> 28) & 0xff;
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+
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+ switch (hawkeye) {
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+ case 0xb7ae:
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+ /* Handle 34xx/35xx devices */
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+ switch (rev) {
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+ case 0: /* Take care of early samples */
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+ case 1:
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+ omap_revision = OMAP3430_REV_ES2_0;
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+ cpu_rev = "2.0";
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+ break;
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+ case 2:
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+ omap_revision = OMAP3430_REV_ES2_1;
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+ cpu_rev = "2.1";
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+ break;
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+ case 3:
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+ omap_revision = OMAP3430_REV_ES3_0;
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+ cpu_rev = "3.0";
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+ break;
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+ case 4:
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+ omap_revision = OMAP3430_REV_ES3_1;
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+ cpu_rev = "3.1";
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+ break;
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+ case 7:
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+ /* FALLTHROUGH */
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+ default:
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+ /* Use the latest known revision as default */
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+ omap_revision = OMAP3430_REV_ES3_1_2;
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+ cpu_rev = "3.1.2";
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+ }
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+ break;
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+ case 0xb868:
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+ /*
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+ * Handle OMAP/AM 3505/3517 devices
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+ *
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+ * Set the device to be OMAP3517 here. Actual device
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+ * is identified later based on the features.
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+ */
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+ switch (rev) {
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+ case 0:
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+ omap_revision = AM35XX_REV_ES1_0;
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+ cpu_rev = "1.0";
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+ break;
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+ case 1:
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+ /* FALLTHROUGH */
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+ default:
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+ omap_revision = AM35XX_REV_ES1_1;
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+ cpu_rev = "1.1";
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+ }
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+ break;
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+ case 0xb891:
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+ /* Handle 36xx devices */
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+
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+ switch(rev) {
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