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@@ -388,3 +388,82 @@ static int __init_or_module omap1_cfg_reg(const struct pin_config *cfg)
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} else {
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} else {
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if (pu_pd_orig & mask)
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if (pu_pd_orig & mask)
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warn = 1;
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warn = 1;
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+ /* Use pull down */
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+ pu_pd = pu_pd_orig & ~mask;
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+ }
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+ omap_writel(pu_pd, cfg->pu_pd_reg);
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+ spin_unlock_irqrestore(&mux_spin_lock, flags);
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+ }
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+ }
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+
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+ /* Check for an associated pull down register */
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+ if (cfg->pull_reg) {
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+ spin_lock_irqsave(&mux_spin_lock, flags);
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+ pull_orig = omap_readl(cfg->pull_reg);
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+ mask = 1 << cfg->pull_bit;
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+
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+ if (cfg->pull_val) {
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+ if (pull_orig & mask)
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+ warn = 1;
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+ /* Low bit = pull enabled */
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+ pull = pull_orig & ~mask;
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+ } else {
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+ if (!(pull_orig & mask))
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+ warn = 1;
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+ /* High bit = pull disabled */
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+ pull = pull_orig | mask;
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+ }
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+
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+ omap_writel(pull, cfg->pull_reg);
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+ spin_unlock_irqrestore(&mux_spin_lock, flags);
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+ }
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+
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+ if (warn) {
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+#ifdef CONFIG_OMAP_MUX_WARNINGS
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+ printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
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+#endif
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+ }
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+
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+#ifdef CONFIG_OMAP_MUX_DEBUG
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+ if (cfg->debug || warn) {
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+ printk("MUX: Setting register %s\n", cfg->name);
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+ printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
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+ cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
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+
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+ if (!cpu_is_omap15xx()) {
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+ if (cfg->pu_pd_reg && cfg->pull_val) {
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+ printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
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+ cfg->pu_pd_name, cfg->pu_pd_reg,
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+ pu_pd_orig, pu_pd);
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+ }
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+ }
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+
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+ if (cfg->pull_reg)
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+ printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
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+ cfg->pull_name, cfg->pull_reg, pull_orig, pull);
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+ }
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+#endif
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+
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+#ifdef CONFIG_OMAP_MUX_WARNINGS
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+ return warn ? -ETXTBSY : 0;
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+#else
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+ return 0;
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+#endif
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+}
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+
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+static struct omap_mux_cfg *mux_cfg;
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+
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+int __init omap_mux_register(struct omap_mux_cfg *arch_mux_cfg)
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+{
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+ if (!arch_mux_cfg || !arch_mux_cfg->pins || arch_mux_cfg->size == 0
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+ || !arch_mux_cfg->cfg_reg) {
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+ printk(KERN_ERR "Invalid pin table\n");
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+ return -EINVAL;
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+ }
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+
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+ mux_cfg = arch_mux_cfg;
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+
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+ return 0;
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+}
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+
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+/*
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