waterHeterogeneousDataSynchronization tcpConnectionMonitoring.h 袁明明 commit at 2021-01-14

waterHeterogeneousDataSynchronization/externalConnectionMonitoring/tcpConnectionMonitoring.h

@@ -692,3 +692,89 @@
 #define B2RAT_10		0x00000A00	/* Bank 2 Read Access Time = 10 cycles */
 #define B2RAT_11		0x00000B00	/* Bank 2 Read Access Time = 11 cycles */
 #define B2RAT_12		0x00000C00	/* Bank 2 Read Access Time = 12 cycles */
+#define B2RAT_13		0x00000D00	/* Bank 2 Read Access Time = 13 cycles */
+#define B2RAT_14		0x00000E00	/* Bank 2 Read Access Time = 14 cycles */
+#define B2RAT_15		0x00000F00	/* Bank 2 Read Access Time = 15 cycles */
+#define B2WAT_1			0x00001000	/* Bank 2 Write Access Time = 1 cycle */
+#define B2WAT_2			0x00002000	/* Bank 2 Write Access Time = 2 cycles */
+#define B2WAT_3			0x00003000	/* Bank 2 Write Access Time = 3 cycles */
+#define B2WAT_4			0x00004000	/* Bank 2 Write Access Time = 4 cycles */
+#define B2WAT_5			0x00005000	/* Bank 2 Write Access Time = 5 cycles */
+#define B2WAT_6			0x00006000	/* Bank 2 Write Access Time = 6 cycles */
+#define B2WAT_7			0x00007000	/* Bank 2 Write Access Time = 7 cycles */
+#define B2WAT_8			0x00008000	/* Bank 2 Write Access Time = 8 cycles */
+#define B2WAT_9			0x00009000	/* Bank 2 Write Access Time = 9 cycles */
+#define B2WAT_10		0x0000A000	/* Bank 2 Write Access Time = 10 cycles */
+#define B2WAT_11		0x0000B000	/* Bank 2 Write Access Time = 11 cycles */
+#define B2WAT_12		0x0000C000	/* Bank 2 Write Access Time = 12 cycles */
+#define B2WAT_13		0x0000D000	/* Bank 2 Write Access Time = 13 cycles */
+#define B2WAT_14		0x0000E000	/* Bank 2 Write Access Time = 14 cycles */
+#define B2WAT_15		0x0000F000	/* Bank 2 Write Access Time = 15 cycles */
+#define B3RDYEN			0x00010000	/* Bank 3 RDY enable, 0=disable, 1=enable */
+#define B3RDYPOL		0x00020000	/* Bank 3 RDY Active high, 0=active low, 1=active high */
+#define B3TT_1			0x00040000	/* Bank 3 Transition Time from Read to Write = 1 cycle */
+#define B3TT_2			0x00080000	/* Bank 3 Transition Time from Read to Write = 2 cycles */
+#define B3TT_3			0x000C0000	/* Bank 3 Transition Time from Read to Write = 3 cycles */
+#define B3TT_4			0x00000000	/* Bank 3 Transition Time from Read to Write = 4 cycles */
+#define B3ST_1			0x00100000	/* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B3ST_2			0x00200000	/* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B3ST_3			0x00300000	/* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B3ST_4			0x00000000	/* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B3HT_1			0x00400000	/* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B3HT_2			0x00800000	/* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B3HT_3			0x00C00000	/* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B3HT_0			0x00000000	/* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
+#define B3RAT_1			0x01000000	/* Bank 3 Read Access Time = 1 cycle */
+#define B3RAT_2			0x02000000	/* Bank 3 Read Access Time = 2 cycles */
+#define B3RAT_3			0x03000000	/* Bank 3 Read Access Time = 3 cycles */
+#define B3RAT_4			0x04000000	/* Bank 3 Read Access Time = 4 cycles */
+#define B3RAT_5			0x05000000	/* Bank 3 Read Access Time = 5 cycles */
+#define B3RAT_6			0x06000000	/* Bank 3 Read Access Time = 6 cycles */
+#define B3RAT_7			0x07000000	/* Bank 3 Read Access Time = 7 cycles */
+#define B3RAT_8			0x08000000	/* Bank 3 Read Access Time = 8 cycles */
+#define B3RAT_9			0x09000000	/* Bank 3 Read Access Time = 9 cycles */
+#define B3RAT_10		0x0A000000	/* Bank 3 Read Access Time = 10 cycles */
+#define B3RAT_11		0x0B000000	/* Bank 3 Read Access Time = 11 cycles */
+#define B3RAT_12		0x0C000000	/* Bank 3 Read Access Time = 12 cycles */
+#define B3RAT_13		0x0D000000	/* Bank 3 Read Access Time = 13 cycles */
+#define B3RAT_14		0x0E000000	/* Bank 3 Read Access Time = 14 cycles */
+#define B3RAT_15		0x0F000000	/* Bank 3 Read Access Time = 15 cycles */
+#define B3WAT_1			0x10000000	/* Bank 3 Write Access Time = 1 cycle */
+#define B3WAT_2			0x20000000	/* Bank 3 Write Access Time = 2 cycles */
+#define B3WAT_3			0x30000000	/* Bank 3 Write Access Time = 3 cycles */
+#define B3WAT_4			0x40000000	/* Bank 3 Write Access Time = 4 cycles */
+#define B3WAT_5			0x50000000	/* Bank 3 Write Access Time = 5 cycles */
+#define B3WAT_6			0x60000000	/* Bank 3 Write Access Time = 6 cycles */
+#define B3WAT_7			0x70000000	/* Bank 3 Write Access Time = 7 cycles */
+#define B3WAT_8			0x80000000	/* Bank 3 Write Access Time = 8 cycles */
+#define B3WAT_9			0x90000000	/* Bank 3 Write Access Time = 9 cycles */
+#define B3WAT_10		0xA0000000	/* Bank 3 Write Access Time = 10 cycles */
+#define B3WAT_11		0xB0000000	/* Bank 3 Write Access Time = 11 cycles */
+#define B3WAT_12		0xC0000000	/* Bank 3 Write Access Time = 12 cycles */
+#define B3WAT_13		0xD0000000	/* Bank 3 Write Access Time = 13 cycles */
+#define B3WAT_14		0xE0000000	/* Bank 3 Write Access Time = 14 cycles */
+#define B3WAT_15		0xF0000000	/* Bank 3 Write Access Time = 15 cycles */
+
+/* **********************  SDRAM CONTROLLER MASKS  *************************** */
+
+/* SDGCTL Masks */
+#define SCTLE			0x00000001	/* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
+#define CL_2			0x00000008	/* SDRAM CAS latency = 2 cycles */
+#define CL_3			0x0000000C	/* SDRAM CAS latency = 3 cycles */
+#define PFE			0x00000010	/* Enable SDRAM prefetch */
+#define PFP			0x00000020	/* Prefetch has priority over AMC requests */
+#define PASR_ALL		0x00000000	/* All 4 SDRAM Banks Refreshed In Self-Refresh				*/
+#define PASR_B0_B1		0x00000010	/* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh		*/
+#define PASR_B0			0x00000020	/* Only SDRAM Bank 0 Is Refreshed In Self-Refresh			*/
+#define TRAS_1			0x00000040	/* SDRAM tRAS = 1 cycle */
+#define TRAS_2			0x00000080	/* SDRAM tRAS = 2 cycles */
+#define TRAS_3			0x000000C0	/* SDRAM tRAS = 3 cycles */
+#define TRAS_4			0x00000100	/* SDRAM tRAS = 4 cycles */
+#define TRAS_5			0x00000140	/* SDRAM tRAS = 5 cycles */
+#define TRAS_6			0x00000180	/* SDRAM tRAS = 6 cycles */
+#define TRAS_7			0x000001C0	/* SDRAM tRAS = 7 cycles */
+#define TRAS_8			0x00000200	/* SDRAM tRAS = 8 cycles */
+#define TRAS_9			0x00000240	/* SDRAM tRAS = 9 cycles */
+#define TRAS_10			0x00000280	/* SDRAM tRAS = 10 cycles */
+#define TRAS_11			0x000002C0	/* SDRAM tRAS = 11 cycles */
+#define TRAS_12			0x00000300	/* SDRAM tRAS = 12 cycles */