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@@ -314,3 +314,81 @@ static struct ads7846_platform_data ads_info = {
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.vref_delay_usecs = 100,
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/* For a 8" touch-screen */
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+ // .x_plate_ohms = 603,
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+ // .y_plate_ohms = 332,
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+
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+ /* For a 10.4" touch-screen */
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+ // .x_plate_ohms = 611,
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+ // .y_plate_ohms = 325,
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+
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+ .x_plate_ohms = 576,
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+ .y_plate_ohms = 366,
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+
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+ .pressure_max = 15000, /* generally nonsense on the 7843 */
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+ .debounce_max = 1,
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+ .debounce_rep = 0,
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+ .debounce_tol = (~0),
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+ .get_pendown_state = ads7843_pendown_state,
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+};
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+
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+static void __init yl9200_add_device_ts(void)
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+{
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+ at91_set_gpio_input(AT91_PIN_PB11, 1); /* Touchscreen interrupt pin */
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+ at91_set_gpio_input(AT91_PIN_PB10, 1); /* Touchscreen BUSY signal - not used! */
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+}
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+#else
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+static void __init yl9200_add_device_ts(void) {}
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+#endif
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+
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+/*
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+ * SPI devices
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+ */
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+static struct spi_board_info yl9200_spi_devices[] = {
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+#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
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+ { /* Touchscreen */
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+ .modalias = "ads7846",
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+ .chip_select = 0,
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+ .max_speed_hz = 5000 * 26,
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+ .platform_data = &ads_info,
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+ .irq = AT91_PIN_PB11,
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+ },
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+#endif
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+ { /* CAN */
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+ .modalias = "mcp2510",
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+ .chip_select = 1,
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+ .max_speed_hz = 25000 * 26,
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+ .irq = AT91_PIN_PC0,
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+ }
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+};
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+
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+/*
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+ * LCD / VGA
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+ *
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+ * EPSON S1D13806 FB (discontinued chip)
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+ * EPSON S1D13506 FB
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+ */
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+#if defined(CONFIG_FB_S1D13XXX) || defined(CONFIG_FB_S1D13XXX_MODULE)
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+#include <video/s1d13xxxfb.h>
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+
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+
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+static void yl9200_init_video(void)
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+{
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+ /* NWAIT Signal */
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+ at91_set_A_periph(AT91_PIN_PC6, 0);
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+
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+ /* Initialization of the Static Memory Controller for Chip Select 2 */
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+ at91_ramc_write(0, AT91_SMC_CSR(2), AT91_SMC_DBW_16 /* 16 bit */
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+ | AT91_SMC_WSEN | AT91_SMC_NWS_(0x4) /* wait states */
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+ | AT91_SMC_TDF_(0x100) /* float time */
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+ );
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+}
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+
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+static struct s1d13xxxfb_regval yl9200_s1dfb_initregs[] =
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+{
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+ {S1DREG_MISC, 0x00}, /* Miscellaneous Register*/
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+ {S1DREG_COM_DISP_MODE, 0x01}, /* Display Mode Register, LCD only*/
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+ {S1DREG_GPIO_CNF0, 0x00}, /* General IO Pins Configuration Register*/
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+ {S1DREG_GPIO_CTL0, 0x00}, /* General IO Pins Control Register*/
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+ {S1DREG_CLK_CNF, 0x11}, /* Memory Clock Configuration Register*/
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+ {S1DREG_LCD_CLK_CNF, 0x10}, /* LCD Pixel Clock Configuration Register*/
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+ {S1DREG_CRT_CLK_CNF, 0x12}, /* CRT/TV Pixel Clock Configuration Register*/
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