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@@ -199,3 +199,116 @@ static u32 _divisor_to_clksel(struct clk_hw_omap *clk, u32 div)
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*/
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static u32 _read_divisor(struct clk_hw_omap *clk)
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{
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+ u32 v;
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+
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+ if (!clk->clksel || !clk->clksel_mask)
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+ return 0;
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+
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+ v = __raw_readl(clk->clksel_reg);
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+ v &= clk->clksel_mask;
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+ v >>= __ffs(clk->clksel_mask);
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+
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+ return _clksel_to_divisor(clk, v);
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+}
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+
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+/* Public functions */
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+
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+/**
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+ * omap2_clksel_round_rate_div() - find divisor for the given clock and rate
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+ * @clk: OMAP struct clk to use
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+ * @target_rate: desired clock rate
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+ * @new_div: ptr to where we should store the divisor
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+ *
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+ * Finds 'best' divider value in an array based on the source and target
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+ * rates. The divider array must be sorted with smallest divider first.
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+ * This function is also used by the DPLL3 M2 divider code.
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+ *
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+ * Returns the rounded clock rate or returns 0xffffffff on error.
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+ */
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+u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk,
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+ unsigned long target_rate,
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+ u32 *new_div)
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+{
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+ unsigned long test_rate;
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+ const struct clksel *clks;
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+ const struct clksel_rate *clkr;
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+ u32 last_div = 0;
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+ struct clk *parent;
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+ unsigned long parent_rate;
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+ const char *clk_name;
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+
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+ parent = __clk_get_parent(clk->hw.clk);
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+ clk_name = __clk_get_name(clk->hw.clk);
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+ parent_rate = __clk_get_rate(parent);
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+
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+ if (!clk->clksel || !clk->clksel_mask)
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+ return ~0;
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+
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+ pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n",
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+ clk_name, target_rate);
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+
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+ *new_div = 1;
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+
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+ clks = _get_clksel_by_parent(clk, parent);
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+ if (!clks)
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+ return ~0;
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+
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+ for (clkr = clks->rates; clkr->div; clkr++) {
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+ if (!(clkr->flags & cpu_mask))
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+ continue;
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+
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+ /* Sanity check */
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+ if (clkr->div <= last_div)
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+ pr_err("clock: %s: clksel_rate table not sorted\n",
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+ clk_name);
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+
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+ last_div = clkr->div;
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+
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+ test_rate = parent_rate / clkr->div;
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+
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+ if (test_rate <= target_rate)
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+ break; /* found it */
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+ }
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+
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+ if (!clkr->div) {
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+ pr_err("clock: %s: could not find divisor for target rate %ld for parent %s\n",
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+ clk_name, target_rate, __clk_get_name(parent));
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+ return ~0;
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+ }
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+
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+ *new_div = clkr->div;
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+
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+ pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div,
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+ (parent_rate / clkr->div));
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+
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+ return parent_rate / clkr->div;
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+}
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+
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+/*
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+ * Clocktype interface functions to the OMAP clock code
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+ * (i.e., those used in struct clk field function pointers, etc.)
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+ */
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+
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+/**
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+ * omap2_clksel_find_parent_index() - return the array index of the current
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+ * hardware parent of @hw
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+ * @hw: struct clk_hw * to find the current hardware parent of
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+ *
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+ * Given a struct clk_hw pointer @hw to the 'hw' member of a struct
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+ * clk_hw_omap record representing a source-selectable hardware clock,
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+ * read the hardware register and determine what its parent is
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+ * currently set to. Intended to be called only by the common clock
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+ * framework struct clk_hw_ops.get_parent function pointer. Return
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+ * the array index of this parent clock upon success -- there is no
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+ * way to return an error, so if we encounter an error, just WARN()
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+ * and pretend that we know that we're doing.
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+ */
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+u8 omap2_clksel_find_parent_index(struct clk_hw *hw)
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+{
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+ struct clk_hw_omap *clk = to_clk_hw_omap(hw);
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+ const struct clksel *clks;
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+ const struct clksel_rate *clkr;
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+ u32 r, found = 0;
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+ struct clk *parent;
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+ const char *clk_name;
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+ int ret = 0, f = 0;
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宁志军