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				@@ -187,3 +187,50 @@ 
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				 /* 
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				  * Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST, 
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				+ * PM_WKUP_PWRSTST, PM_RTC_PWRSTST 
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				+ */ 
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				+#define AM33XX_LOGICSTATEST_SHIFT			2 
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				+#define AM33XX_LOGICSTATEST_MASK			(1 << 2) 
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				+ 
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				+/* 
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				+ * Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL, 
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				+ * PM_MPU_PWRSTCTRL, PM_WKUP_PWRSTCTRL, PM_RTC_PWRSTCTRL 
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				+ */ 
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				+#define AM33XX_LOWPOWERSTATECHANGE_SHIFT		4 
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				+#define AM33XX_LOWPOWERSTATECHANGE_MASK			(1 << 4) 
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				+ 
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				+/* Used by PM_MPU_PWRSTCTRL */ 
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				+#define AM33XX_MPU_L1_ONSTATE_SHIFT			18 
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				+#define AM33XX_MPU_L1_ONSTATE_MASK			(0x3 << 18) 
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				+ 
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				+/* Used by PM_MPU_PWRSTCTRL */ 
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				+#define AM33XX_MPU_L1_RETSTATE_SHIFT			22 
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				+#define AM33XX_MPU_L1_RETSTATE_MASK			(1 << 22) 
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				+ 
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				+/* Used by PM_MPU_PWRSTST */ 
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				+#define AM33XX_MPU_L1_STATEST_SHIFT			6 
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				+#define AM33XX_MPU_L1_STATEST_MASK			(0x3 << 6) 
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				+ 
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				+/* Used by PM_MPU_PWRSTCTRL */ 
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				+#define AM33XX_MPU_L2_ONSTATE_SHIFT			20 
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				+#define AM33XX_MPU_L2_ONSTATE_MASK			(0x3 << 20) 
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				+ 
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				+/* Used by PM_MPU_PWRSTCTRL */ 
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				+#define AM33XX_MPU_L2_RETSTATE_SHIFT			23 
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				+#define AM33XX_MPU_L2_RETSTATE_MASK			(1 << 23) 
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				+ 
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				+/* Used by PM_MPU_PWRSTST */ 
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				+#define AM33XX_MPU_L2_STATEST_SHIFT			8 
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				+#define AM33XX_MPU_L2_STATEST_MASK			(0x3 << 8) 
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				+ 
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				+/* Used by PM_MPU_PWRSTCTRL */ 
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				+#define AM33XX_MPU_RAM_ONSTATE_SHIFT			16 
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				+#define AM33XX_MPU_RAM_ONSTATE_MASK			(0x3 << 16) 
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				+ 
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				+/* Used by PM_MPU_PWRSTCTRL */ 
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				+#define AM33XX_MPU_RAM_RETSTATE_SHIFT			24 
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				+#define AM33XX_MPU_RAM_RETSTATE_MASK			(1 << 24) 
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				+ 
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				+/* Used by PM_MPU_PWRSTST */ 
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				+#define AM33XX_MPU_RAM_STATEST_SHIFT			4 
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				+#define AM33XX_MPU_RAM_STATEST_MASK			(0x3 << 4) 
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