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+/*
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+ * Copyright (C) 2009 Nokia
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+ * Copyright (C) 2009 Texas Instruments
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ */
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+
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+#define OMAP2420_CONTROL_PADCONF_MUX_PBASE 0x48000030LU
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+
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+#define OMAP2420_MUX(mode0, mux_value) \
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+{ \
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+ .reg_offset = (OMAP2420_CONTROL_PADCONF_##mode0##_OFFSET), \
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+ .value = (mux_value), \
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+}
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+
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+/*
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+ * OMAP2420 CONTROL_PADCONF* register offsets for pin-muxing
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+ *
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+ * Extracted from the TRM. Add 0x48000030 to these values to get the
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+ * absolute addresses. The name in the macro is the mode-0 name of
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+ * the pin. NOTE: These registers are 8-bits wide.
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+ */
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+#define OMAP2420_CONTROL_PADCONF_SDRC_A14_OFFSET 0x000
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+#define OMAP2420_CONTROL_PADCONF_SDRC_A13_OFFSET 0x001
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+#define OMAP2420_CONTROL_PADCONF_SDRC_A12_OFFSET 0x002
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+#define OMAP2420_CONTROL_PADCONF_SDRC_BA1_OFFSET 0x003
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+#define OMAP2420_CONTROL_PADCONF_SDRC_BA0_OFFSET 0x004
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+#define OMAP2420_CONTROL_PADCONF_SDRC_A11_OFFSET 0x005
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+#define OMAP2420_CONTROL_PADCONF_SDRC_A10_OFFSET 0x006
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+#define OMAP2420_CONTROL_PADCONF_SDRC_A9_OFFSET 0x007
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+#define OMAP2420_CONTROL_PADCONF_SDRC_A8_OFFSET 0x008
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+#define OMAP2420_CONTROL_PADCONF_SDRC_A7_OFFSET 0x009
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+#define OMAP2420_CONTROL_PADCONF_SDRC_A6_OFFSET 0x00a
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+#define OMAP2420_CONTROL_PADCONF_SDRC_A5_OFFSET 0x00b
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+#define OMAP2420_CONTROL_PADCONF_SDRC_A4_OFFSET 0x00c
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+#define OMAP2420_CONTROL_PADCONF_SDRC_A3_OFFSET 0x00d
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+#define OMAP2420_CONTROL_PADCONF_SDRC_A2_OFFSET 0x00e
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+#define OMAP2420_CONTROL_PADCONF_SDRC_A1_OFFSET 0x00f
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+#define OMAP2420_CONTROL_PADCONF_SDRC_A0_OFFSET 0x010
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+#define OMAP2420_CONTROL_PADCONF_SDRC_D31_OFFSET 0x021
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+#define OMAP2420_CONTROL_PADCONF_SDRC_D30_OFFSET 0x022
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+#define OMAP2420_CONTROL_PADCONF_SDRC_D29_OFFSET 0x023
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+#define OMAP2420_CONTROL_PADCONF_SDRC_D28_OFFSET 0x024
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+#define OMAP2420_CONTROL_PADCONF_SDRC_D27_OFFSET 0x025
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+#define OMAP2420_CONTROL_PADCONF_SDRC_D26_OFFSET 0x026
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+#define OMAP2420_CONTROL_PADCONF_SDRC_D25_OFFSET 0x027
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+#define OMAP2420_CONTROL_PADCONF_SDRC_D24_OFFSET 0x028
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+#define OMAP2420_CONTROL_PADCONF_SDRC_D23_OFFSET 0x029
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+#define OMAP2420_CONTROL_PADCONF_SDRC_D22_OFFSET 0x02a
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+#define OMAP2420_CONTROL_PADCONF_SDRC_D21_OFFSET 0x02b
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+#define OMAP2420_CONTROL_PADCONF_SDRC_D20_OFFSET 0x02c
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+#define OMAP2420_CONTROL_PADCONF_SDRC_D19_OFFSET 0x02d
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+#define OMAP2420_CONTROL_PADCONF_SDRC_D18_OFFSET 0x02e
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+#define OMAP2420_CONTROL_PADCONF_SDRC_D17_OFFSET 0x02f
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+#define OMAP2420_CONTROL_PADCONF_SDRC_D16_OFFSET 0x030
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+#define OMAP2420_CONTROL_PADCONF_SDRC_D15_OFFSET 0x031
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+#define OMAP2420_CONTROL_PADCONF_SDRC_D14_OFFSET 0x032
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+#define OMAP2420_CONTROL_PADCONF_SDRC_D13_OFFSET 0x033
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+#define OMAP2420_CONTROL_PADCONF_SDRC_D12_OFFSET 0x034
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+#define OMAP2420_CONTROL_PADCONF_SDRC_D11_OFFSET 0x035
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