|
@@ -157,3 +157,116 @@
|
|
#define OMAP4_USB_VENDOR_ID_SHIFT 0
|
|
#define OMAP4_USB_VENDOR_ID_SHIFT 0
|
|
#define OMAP4_USB_VENDOR_ID_MASK (0xffff << 0)
|
|
#define OMAP4_USB_VENDOR_ID_MASK (0xffff << 0)
|
|
|
|
|
|
|
|
+/* STD_FUSE_OPP_VDD_WKUP */
|
|
|
|
+#define OMAP4_STD_FUSE_OPP_VDD_WKUP_SHIFT 0
|
|
|
|
+#define OMAP4_STD_FUSE_OPP_VDD_WKUP_MASK (0xffffffff << 0)
|
|
|
|
+
|
|
|
|
+/* STD_FUSE_OPP_BGAP */
|
|
|
|
+#define OMAP4_STD_FUSE_OPP_BGAP_SHIFT 0
|
|
|
|
+#define OMAP4_STD_FUSE_OPP_BGAP_MASK (0xffffffff << 0)
|
|
|
|
+
|
|
|
|
+/* STD_FUSE_OPP_DPLL_0 */
|
|
|
|
+#define OMAP4_STD_FUSE_OPP_DPLL_0_SHIFT 0
|
|
|
|
+#define OMAP4_STD_FUSE_OPP_DPLL_0_MASK (0xffffffff << 0)
|
|
|
|
+
|
|
|
|
+/* STD_FUSE_OPP_DPLL_1 */
|
|
|
|
+#define OMAP4_STD_FUSE_OPP_DPLL_1_SHIFT 0
|
|
|
|
+#define OMAP4_STD_FUSE_OPP_DPLL_1_MASK (0xffffffff << 0)
|
|
|
|
+
|
|
|
|
+/* STATUS */
|
|
|
|
+#define OMAP4_ATTILA_CONF_SHIFT 11
|
|
|
|
+#define OMAP4_ATTILA_CONF_MASK (0x3 << 11)
|
|
|
|
+#define OMAP4_DEVICE_TYPE_SHIFT 8
|
|
|
|
+#define OMAP4_DEVICE_TYPE_MASK (0x7 << 8)
|
|
|
|
+#define OMAP4_SYS_BOOT_SHIFT 0
|
|
|
|
+#define OMAP4_SYS_BOOT_MASK (0xff << 0)
|
|
|
|
+
|
|
|
|
+/* DEV_CONF */
|
|
|
|
+#define OMAP4_DEV_CONF_SHIFT 1
|
|
|
|
+#define OMAP4_DEV_CONF_MASK (0x7fffffff << 1)
|
|
|
|
+#define OMAP4_USBPHY_PD_SHIFT 0
|
|
|
|
+#define OMAP4_USBPHY_PD_MASK (1 << 0)
|
|
|
|
+
|
|
|
|
+/* LDOVBB_IVA_VOLTAGE_CTRL */
|
|
|
|
+#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_SHIFT 26
|
|
|
|
+#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_MASK (1 << 26)
|
|
|
|
+#define OMAP4_LDOVBBIVA_RBB_VSET_IN_SHIFT 21
|
|
|
|
+#define OMAP4_LDOVBBIVA_RBB_VSET_IN_MASK (0x1f << 21)
|
|
|
|
+#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_SHIFT 16
|
|
|
|
+#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_MASK (0x1f << 16)
|
|
|
|
+#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_SHIFT 10
|
|
|
|
+#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_MASK (1 << 10)
|
|
|
|
+#define OMAP4_LDOVBBIVA_FBB_VSET_IN_SHIFT 5
|
|
|
|
+#define OMAP4_LDOVBBIVA_FBB_VSET_IN_MASK (0x1f << 5)
|
|
|
|
+#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_SHIFT 0
|
|
|
|
+#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_MASK (0x1f << 0)
|
|
|
|
+
|
|
|
|
+/* LDOVBB_MPU_VOLTAGE_CTRL */
|
|
|
|
+#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_SHIFT 26
|
|
|
|
+#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_MASK (1 << 26)
|
|
|
|
+#define OMAP4_LDOVBBMPU_RBB_VSET_IN_SHIFT 21
|
|
|
|
+#define OMAP4_LDOVBBMPU_RBB_VSET_IN_MASK (0x1f << 21)
|
|
|
|
+#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_SHIFT 16
|
|
|
|
+#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_MASK (0x1f << 16)
|
|
|
|
+#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_SHIFT 10
|
|
|
|
+#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_MASK (1 << 10)
|
|
|
|
+#define OMAP4_LDOVBBMPU_FBB_VSET_IN_SHIFT 5
|
|
|
|
+#define OMAP4_LDOVBBMPU_FBB_VSET_IN_MASK (0x1f << 5)
|
|
|
|
+#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_SHIFT 0
|
|
|
|
+#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_MASK (0x1f << 0)
|
|
|
|
+
|
|
|
|
+/* LDOSRAM_IVA_VOLTAGE_CTRL */
|
|
|
|
+#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_SHIFT 26
|
|
|
|
+#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_MASK (1 << 26)
|
|
|
|
+#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_SHIFT 21
|
|
|
|
+#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_MASK (0x1f << 21)
|
|
|
|
+#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_SHIFT 16
|
|
|
|
+#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_MASK (0x1f << 16)
|
|
|
|
+#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_SHIFT 10
|
|
|
|
+#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_MASK (1 << 10)
|
|
|
|
+#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_SHIFT 5
|
|
|
|
+#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_MASK (0x1f << 5)
|
|
|
|
+#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_SHIFT 0
|
|
|
|
+#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_MASK (0x1f << 0)
|
|
|
|
+
|
|
|
|
+/* LDOSRAM_MPU_VOLTAGE_CTRL */
|
|
|
|
+#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_SHIFT 26
|
|
|
|
+#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_MASK (1 << 26)
|
|
|
|
+#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_SHIFT 21
|
|
|
|
+#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_MASK (0x1f << 21)
|
|
|
|
+#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_SHIFT 16
|
|
|
|
+#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_MASK (0x1f << 16)
|
|
|
|
+#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_SHIFT 10
|
|
|
|
+#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_MASK (1 << 10)
|
|
|
|
+#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_SHIFT 5
|
|
|
|
+#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_MASK (0x1f << 5)
|
|
|
|
+#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_SHIFT 0
|
|
|
|
+#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_MASK (0x1f << 0)
|
|
|
|
+
|
|
|
|
+/* LDOSRAM_CORE_VOLTAGE_CTRL */
|
|
|
|
+#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_SHIFT 26
|
|
|
|
+#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_MASK (1 << 26)
|
|
|
|
+#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_SHIFT 21
|
|
|
|
+#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_MASK (0x1f << 21)
|
|
|
|
+#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_SHIFT 16
|
|
|
|
+#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_MASK (0x1f << 16)
|
|
|
|
+#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_SHIFT 10
|
|
|
|
+#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_MASK (1 << 10)
|
|
|
|
+#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_SHIFT 5
|
|
|
|
+#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_MASK (0x1f << 5)
|
|
|
|
+#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_SHIFT 0
|
|
|
|
+#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_MASK (0x1f << 0)
|
|
|
|
+
|
|
|
|
+/* TEMP_SENSOR */
|
|
|
|
+#define OMAP4_BGAP_TEMPSOFF_SHIFT 12
|
|
|
|
+#define OMAP4_BGAP_TEMPSOFF_MASK (1 << 12)
|
|
|
|
+#define OMAP4_BGAP_TSHUT_SHIFT 11
|
|
|
|
+#define OMAP4_BGAP_TSHUT_MASK (1 << 11)
|
|
|
|
+#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_SHIFT 10
|
|
|
|
+#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_MASK (1 << 10)
|
|
|
|
+#define OMAP4_BGAP_TEMP_SENSOR_SOC_SHIFT 9
|
|
|
|
+#define OMAP4_BGAP_TEMP_SENSOR_SOC_MASK (1 << 9)
|
|
|
|
+#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_SHIFT 8
|
|
|
|
+#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_MASK (1 << 8)
|
|
|
|
+#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_SHIFT 0
|
|
|
|
+#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_MASK (0xff << 0)
|