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@@ -582,3 +582,71 @@
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#define USIR0_IR4 (1 << 4) /* Interrupt request ep 4 */
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#define USIR0_IR4 (1 << 4) /* Interrupt request ep 4 */
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#define USIR0_IR5 (1 << 5) /* Interrupt request ep 5 */
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#define USIR0_IR5 (1 << 5) /* Interrupt request ep 5 */
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#define USIR0_IR6 (1 << 6) /* Interrupt request ep 6 */
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#define USIR0_IR6 (1 << 6) /* Interrupt request ep 6 */
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+#define USIR0_IR7 (1 << 7) /* Interrupt request ep 7 */
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+
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+#define USIR1_IR8 (1 << 0) /* Interrupt request ep 8 */
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+#define USIR1_IR9 (1 << 1) /* Interrupt request ep 9 */
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+#define USIR1_IR10 (1 << 2) /* Interrupt request ep 10 */
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+#define USIR1_IR11 (1 << 3) /* Interrupt request ep 11 */
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+#define USIR1_IR12 (1 << 4) /* Interrupt request ep 12 */
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+#define USIR1_IR13 (1 << 5) /* Interrupt request ep 13 */
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+#define USIR1_IR14 (1 << 6) /* Interrupt request ep 14 */
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+#define USIR1_IR15 (1 << 7) /* Interrupt request ep 15 */
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+
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+#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
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+
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+/* "fuse" bits of IXP_EXP_CFG2 */
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+/* All IXP4xx CPUs */
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+#define IXP4XX_FEATURE_RCOMP (1 << 0)
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+#define IXP4XX_FEATURE_USB_DEVICE (1 << 1)
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+#define IXP4XX_FEATURE_HASH (1 << 2)
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+#define IXP4XX_FEATURE_AES (1 << 3)
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+#define IXP4XX_FEATURE_DES (1 << 4)
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+#define IXP4XX_FEATURE_HDLC (1 << 5)
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+#define IXP4XX_FEATURE_AAL (1 << 6)
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+#define IXP4XX_FEATURE_HSS (1 << 7)
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+#define IXP4XX_FEATURE_UTOPIA (1 << 8)
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+#define IXP4XX_FEATURE_NPEB_ETH0 (1 << 9)
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+#define IXP4XX_FEATURE_NPEC_ETH (1 << 10)
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+#define IXP4XX_FEATURE_RESET_NPEA (1 << 11)
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+#define IXP4XX_FEATURE_RESET_NPEB (1 << 12)
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+#define IXP4XX_FEATURE_RESET_NPEC (1 << 13)
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+#define IXP4XX_FEATURE_PCI (1 << 14)
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+#define IXP4XX_FEATURE_UTOPIA_PHY_LIMIT (3 << 16)
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+#define IXP4XX_FEATURE_XSCALE_MAX_FREQ (3 << 22)
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+#define IXP42X_FEATURE_MASK (IXP4XX_FEATURE_RCOMP | \
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+ IXP4XX_FEATURE_USB_DEVICE | \
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+ IXP4XX_FEATURE_HASH | \
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+ IXP4XX_FEATURE_AES | \
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+ IXP4XX_FEATURE_DES | \
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+ IXP4XX_FEATURE_HDLC | \
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+ IXP4XX_FEATURE_AAL | \
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+ IXP4XX_FEATURE_HSS | \
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+ IXP4XX_FEATURE_UTOPIA | \
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+ IXP4XX_FEATURE_NPEB_ETH0 | \
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+ IXP4XX_FEATURE_NPEC_ETH | \
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+ IXP4XX_FEATURE_RESET_NPEA | \
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+ IXP4XX_FEATURE_RESET_NPEB | \
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+ IXP4XX_FEATURE_RESET_NPEC | \
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+ IXP4XX_FEATURE_PCI | \
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+ IXP4XX_FEATURE_UTOPIA_PHY_LIMIT | \
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+ IXP4XX_FEATURE_XSCALE_MAX_FREQ)
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+
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+
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+/* IXP43x/46x CPUs */
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+#define IXP4XX_FEATURE_ECC_TIMESYNC (1 << 15)
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+#define IXP4XX_FEATURE_USB_HOST (1 << 18)
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+#define IXP4XX_FEATURE_NPEA_ETH (1 << 19)
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+#define IXP43X_FEATURE_MASK (IXP42X_FEATURE_MASK | \
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+ IXP4XX_FEATURE_ECC_TIMESYNC | \
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+ IXP4XX_FEATURE_USB_HOST | \
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+ IXP4XX_FEATURE_NPEA_ETH)
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+
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+/* IXP46x CPU (including IXP455) only */
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+#define IXP4XX_FEATURE_NPEB_ETH_1_TO_3 (1 << 20)
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+#define IXP4XX_FEATURE_RSA (1 << 21)
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+#define IXP46X_FEATURE_MASK (IXP43X_FEATURE_MASK | \
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+ IXP4XX_FEATURE_NPEB_ETH_1_TO_3 | \
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+ IXP4XX_FEATURE_RSA)
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+
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+#endif
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