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				|  |  | +/*
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				|  |  | + * Copyright 2005-2010 Analog Devices Inc.
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				|  |  | + *
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				|  |  | + * Licensed under the Clear BSD license or the GPL-2 (or later)
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				|  |  | + */
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				|  |  | +
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				|  |  | +#ifndef _DEF_BF534_H
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				|  |  | +#define _DEF_BF534_H
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				|  |  | +
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				|  |  | +/************************************************************************************
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				|  |  | +** System MMR Register Map
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				|  |  | +*************************************************************************************/
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				|  |  | +/* Clock and System Control	(0xFFC00000 - 0xFFC000FF)								*/
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				|  |  | +#define PLL_CTL				0xFFC00000	/* PLL Control Register                                         */
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				|  |  | +#define PLL_DIV				0xFFC00004	/* PLL Divide Register                                          */
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				|  |  | +#define VR_CTL				0xFFC00008	/* Voltage Regulator Control Register           */
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				|  |  | +#define PLL_STAT			0xFFC0000C	/* PLL Status Register                                          */
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				|  |  | +#define PLL_LOCKCNT			0xFFC00010	/* PLL Lock Count Register                                      */
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				|  |  | +#define CHIPID				0xFFC00014      /* Chip ID Register                                             */
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				|  |  | +
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				|  |  | +/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)							*/
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				|  |  | +#define SWRST				0xFFC00100	/* Software Reset Register                                      */
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				|  |  | +#define SYSCR				0xFFC00104	/* System Configuration Register                        */
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				|  |  | +#define SIC_RVECT			0xFFC00108	/* Interrupt Reset Vector Address Register      */
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				|  |  | +#define SIC_IMASK			0xFFC0010C	/* Interrupt Mask Register                                      */
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				|  |  | +#define SIC_IAR0			0xFFC00110	/* Interrupt Assignment Register 0                      */
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				|  |  | +#define SIC_IAR1			0xFFC00114	/* Interrupt Assignment Register 1                      */
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				|  |  | +#define SIC_IAR2			0xFFC00118	/* Interrupt Assignment Register 2                      */
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				|  |  | +#define SIC_IAR3			0xFFC0011C	/* Interrupt Assignment Register 3                      */
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				|  |  | +#define SIC_ISR				0xFFC00120	/* Interrupt Status Register                            */
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				|  |  | +#define SIC_IWR				0xFFC00124	/* Interrupt Wakeup Register                            */
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				|  |  | +
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