waterDataStatisticsCrossAssociation commandProcessing.h 袁明明 commit at 2020-12-21

waterDataStatisticsCrossAssociation/externalListeningThread/commandProcessing.h

@@ -1864,3 +1864,114 @@
 /* =========================
         DMA17
    ========================= */
+#define DMA17_NEXT_DESC_PTR            0xFFC07200         /* DMA17 Pointer to Next Initial Descriptor */
+#define DMA17_START_ADDR             0xFFC07204         /* DMA17 Start Address of Current Buffer */
+#define DMA17_CONFIG                   0xFFC07208         /* DMA17 Configuration Register */
+#define DMA17_X_COUNT                  0xFFC0720C         /* DMA17 Inner Loop Count Start Value */
+#define DMA17_X_MODIFY                  0xFFC07210         /* DMA17 Inner Loop Address Increment */
+#define DMA17_Y_COUNT                  0xFFC07214         /* DMA17 Outer Loop Count Start Value (2D only) */
+#define DMA17_Y_MODIFY                  0xFFC07218         /* DMA17 Outer Loop Address Increment (2D only) */
+#define DMA17_CURR_DESC_PTR            0xFFC07224         /* DMA17 Current Descriptor Pointer */
+#define DMA17_PREV_DESC_PTR            0xFFC07228         /* DMA17 Previous Initial Descriptor Pointer */
+#define DMA17_CURR_ADDR              0xFFC0722C         /* DMA17 Current Address */
+#define DMA17_IRQ_STATUS                  0xFFC07230         /* DMA17 Status Register */
+#define DMA17_CURR_X_COUNT              0xFFC07234         /* DMA17 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA17_CURR_Y_COUNT              0xFFC07238         /* DMA17 Current Row Count (2D only) */
+#define DMA17_BWL_COUNT                0xFFC07240         /* DMA17 Bandwidth Limit Count */
+#define DMA17_CURR_BWL_COUNT            0xFFC07244         /* DMA17 Bandwidth Limit Count Current */
+#define DMA17_BWM_COUNT                0xFFC07248         /* DMA17 Bandwidth Monitor Count */
+#define DMA17_CURR_BWM_COUNT            0xFFC0724C         /* DMA17 Bandwidth Monitor Count Current */
+
+/* =========================
+        DMA18
+   ========================= */
+#define DMA18_NEXT_DESC_PTR            0xFFC07280         /* DMA18 Pointer to Next Initial Descriptor */
+#define DMA18_START_ADDR             0xFFC07284         /* DMA18 Start Address of Current Buffer */
+#define DMA18_CONFIG                   0xFFC07288         /* DMA18 Configuration Register */
+#define DMA18_X_COUNT                  0xFFC0728C         /* DMA18 Inner Loop Count Start Value */
+#define DMA18_X_MODIFY                  0xFFC07290         /* DMA18 Inner Loop Address Increment */
+#define DMA18_Y_COUNT                  0xFFC07294         /* DMA18 Outer Loop Count Start Value (2D only) */
+#define DMA18_Y_MODIFY                  0xFFC07298         /* DMA18 Outer Loop Address Increment (2D only) */
+#define DMA18_CURR_DESC_PTR            0xFFC072A4         /* DMA18 Current Descriptor Pointer */
+#define DMA18_PREV_DESC_PTR            0xFFC072A8         /* DMA18 Previous Initial Descriptor Pointer */
+#define DMA18_CURR_ADDR              0xFFC072AC         /* DMA18 Current Address */
+#define DMA18_IRQ_STATUS                  0xFFC072B0         /* DMA18 Status Register */
+#define DMA18_CURR_X_COUNT              0xFFC072B4         /* DMA18 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA18_CURR_Y_COUNT              0xFFC072B8         /* DMA18 Current Row Count (2D only) */
+#define DMA18_BWL_COUNT                0xFFC072C0         /* DMA18 Bandwidth Limit Count */
+#define DMA18_CURR_BWL_COUNT            0xFFC072C4         /* DMA18 Bandwidth Limit Count Current */
+#define DMA18_BWM_COUNT                0xFFC072C8         /* DMA18 Bandwidth Monitor Count */
+#define DMA18_CURR_BWM_COUNT            0xFFC072CC         /* DMA18 Bandwidth Monitor Count Current */
+
+/* =========================
+        DMA19
+   ========================= */
+#define DMA19_NEXT_DESC_PTR            0xFFC07300         /* DMA19 Pointer to Next Initial Descriptor */
+#define DMA19_START_ADDR             0xFFC07304         /* DMA19 Start Address of Current Buffer */
+#define DMA19_CONFIG                   0xFFC07308         /* DMA19 Configuration Register */
+#define DMA19_X_COUNT                  0xFFC0730C         /* DMA19 Inner Loop Count Start Value */
+#define DMA19_X_MODIFY                  0xFFC07310         /* DMA19 Inner Loop Address Increment */
+#define DMA19_Y_COUNT                  0xFFC07314         /* DMA19 Outer Loop Count Start Value (2D only) */
+#define DMA19_Y_MODIFY                  0xFFC07318         /* DMA19 Outer Loop Address Increment (2D only) */
+#define DMA19_CURR_DESC_PTR            0xFFC07324         /* DMA19 Current Descriptor Pointer */
+#define DMA19_PREV_DESC_PTR            0xFFC07328         /* DMA19 Previous Initial Descriptor Pointer */
+#define DMA19_CURR_ADDR              0xFFC0732C         /* DMA19 Current Address */
+#define DMA19_IRQ_STATUS                  0xFFC07330         /* DMA19 Status Register */
+#define DMA19_CURR_X_COUNT              0xFFC07334         /* DMA19 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA19_CURR_Y_COUNT              0xFFC07338         /* DMA19 Current Row Count (2D only) */
+#define DMA19_BWL_COUNT                0xFFC07340         /* DMA19 Bandwidth Limit Count */
+#define DMA19_CURR_BWL_COUNT            0xFFC07344         /* DMA19 Bandwidth Limit Count Current */
+#define DMA19_BWM_COUNT                0xFFC07348         /* DMA19 Bandwidth Monitor Count */
+#define DMA19_CURR_BWM_COUNT            0xFFC0734C         /* DMA19 Bandwidth Monitor Count Current */
+
+/* =========================
+        DMA20
+   ========================= */
+#define DMA20_NEXT_DESC_PTR            0xFFC07380         /* DMA20 Pointer to Next Initial Descriptor */
+#define DMA20_START_ADDR             0xFFC07384         /* DMA20 Start Address of Current Buffer */
+#define DMA20_CONFIG                   0xFFC07388         /* DMA20 Configuration Register */
+#define DMA20_X_COUNT                  0xFFC0738C         /* DMA20 Inner Loop Count Start Value */
+#define DMA20_X_MODIFY                  0xFFC07390         /* DMA20 Inner Loop Address Increment */
+#define DMA20_Y_COUNT                  0xFFC07394         /* DMA20 Outer Loop Count Start Value (2D only) */
+#define DMA20_Y_MODIFY                  0xFFC07398         /* DMA20 Outer Loop Address Increment (2D only) */
+#define DMA20_CURR_DESC_PTR            0xFFC073A4         /* DMA20 Current Descriptor Pointer */
+#define DMA20_PREV_DESC_PTR            0xFFC073A8         /* DMA20 Previous Initial Descriptor Pointer */
+#define DMA20_CURR_ADDR              0xFFC073AC         /* DMA20 Current Address */
+#define DMA20_IRQ_STATUS                  0xFFC073B0         /* DMA20 Status Register */
+#define DMA20_CURR_X_COUNT              0xFFC073B4         /* DMA20 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA20_CURR_Y_COUNT              0xFFC073B8         /* DMA20 Current Row Count (2D only) */
+#define DMA20_BWL_COUNT                0xFFC073C0         /* DMA20 Bandwidth Limit Count */
+#define DMA20_CURR_BWL_COUNT            0xFFC073C4         /* DMA20 Bandwidth Limit Count Current */
+#define DMA20_BWM_COUNT                0xFFC073C8         /* DMA20 Bandwidth Monitor Count */
+#define DMA20_CURR_BWM_COUNT            0xFFC073CC         /* DMA20 Bandwidth Monitor Count Current */
+
+/* =========================
+        DMA21
+   ========================= */
+#define DMA21_NEXT_DESC_PTR            0xFFC09000         /* DMA21 Pointer to Next Initial Descriptor */
+#define DMA21_START_ADDR             0xFFC09004         /* DMA21 Start Address of Current Buffer */
+#define DMA21_CONFIG                   0xFFC09008         /* DMA21 Configuration Register */
+#define DMA21_X_COUNT                  0xFFC0900C         /* DMA21 Inner Loop Count Start Value */
+#define DMA21_X_MODIFY                  0xFFC09010         /* DMA21 Inner Loop Address Increment */
+#define DMA21_Y_COUNT                  0xFFC09014         /* DMA21 Outer Loop Count Start Value (2D only) */
+#define DMA21_Y_MODIFY                  0xFFC09018         /* DMA21 Outer Loop Address Increment (2D only) */
+#define DMA21_CURR_DESC_PTR            0xFFC09024         /* DMA21 Current Descriptor Pointer */
+#define DMA21_PREV_DESC_PTR            0xFFC09028         /* DMA21 Previous Initial Descriptor Pointer */
+#define DMA21_CURR_ADDR              0xFFC0902C         /* DMA21 Current Address */
+#define DMA21_IRQ_STATUS                  0xFFC09030         /* DMA21 Status Register */
+#define DMA21_CURR_X_COUNT              0xFFC09034         /* DMA21 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA21_CURR_Y_COUNT              0xFFC09038         /* DMA21 Current Row Count (2D only) */
+#define DMA21_BWL_COUNT                0xFFC09040         /* DMA21 Bandwidth Limit Count */
+#define DMA21_CURR_BWL_COUNT            0xFFC09044         /* DMA21 Bandwidth Limit Count Current */
+#define DMA21_BWM_COUNT                0xFFC09048         /* DMA21 Bandwidth Monitor Count */
+#define DMA21_CURR_BWM_COUNT            0xFFC0904C         /* DMA21 Bandwidth Monitor Count Current */
+
+/* =========================
+        DMA22
+   ========================= */
+#define DMA22_NEXT_DESC_PTR            0xFFC09080         /* DMA22 Pointer to Next Initial Descriptor */
+#define DMA22_START_ADDR             0xFFC09084         /* DMA22 Start Address of Current Buffer */
+#define DMA22_CONFIG                   0xFFC09088         /* DMA22 Configuration Register */
+#define DMA22_X_COUNT                  0xFFC0908C         /* DMA22 Inner Loop Count Start Value */
+#define DMA22_X_MODIFY                  0xFFC09090         /* DMA22 Inner Loop Address Increment */
+#define DMA22_Y_COUNT                  0xFFC09094         /* DMA22 Outer Loop Count Start Value (2D only) */