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@@ -434,3 +434,180 @@
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#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
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#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP,val)
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+#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
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+#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG,val)
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+#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
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+#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR,val)
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+#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
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+#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR,val)
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+#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
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+#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT,val)
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+#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
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+#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT,val)
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+#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
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+#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY,val)
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+#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
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+#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY,val)
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+#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
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+#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR,val)
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+#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
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+#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR,val)
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+#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
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+#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT,val)
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+#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
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+#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT,val)
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+#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
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+#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS,val)
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+#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
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+#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP,val)
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+
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+#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
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+#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG,val)
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+#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
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+#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR,val)
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+#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
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+#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR,val)
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+#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
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+#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT,val)
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+#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
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+#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT,val)
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+#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
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+#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY,val)
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+#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
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+#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY,val)
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+#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
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+#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR,val)
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+#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
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+#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR,val)
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+#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
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+#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT,val)
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+#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
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+#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT,val)
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+#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
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+#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS,val)
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+#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
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+#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP,val)
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+
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+#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
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+#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG,val)
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+#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
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+#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR,val)
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+#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
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+#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR,val)
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+#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
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+#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT,val)
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+#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
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+#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT,val)
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+#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
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+#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY,val)
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+#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
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+#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY,val)
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+#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
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+#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR,val)
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+#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
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+#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR,val)
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+#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
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+#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT,val)
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+#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
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+#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT,val)
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+#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
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+#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS,val)
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+#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
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+#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP,val)
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+
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+#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
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+#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG,val)
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+#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
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+#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR,val)
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+#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
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+#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR,val)
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+#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
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+#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT,val)
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+#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
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+#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT,val)
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+#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
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+#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY,val)
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+#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
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+#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY,val)
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+#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
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+#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR,val)
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+#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
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+#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR,val)
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+#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
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+#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT,val)
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+#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
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+#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT,val)
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+#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
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+#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS,val)
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+#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
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+#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP,val)
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+
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+#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
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+#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG,val)
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+#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
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+#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR,val)
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+#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
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+#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR,val)
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+#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
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+#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT,val)
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+#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
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+#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT,val)
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+#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
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+#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY,val)
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+#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
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+#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY,val)
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+#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
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+#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR,val)
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+#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
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+#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR,val)
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+#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
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+#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT,val)
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+#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
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+#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT,val)
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+#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
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+#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS,val)
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+#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
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+#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP,val)
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+
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+#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
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+#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG,val)
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+#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
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+#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR,val)
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+#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
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+#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR,val)
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+#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
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+#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT,val)
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+#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
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+#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT,val)
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+#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
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+#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY,val)
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+#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
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+#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY,val)
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+#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
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+#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR,val)
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+#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
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+#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR,val)
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+#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
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+#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT,val)
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+#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
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+#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT,val)
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+#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
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+#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS,val)
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+#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
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+#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP,val)
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+
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+#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
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+#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG,val)
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+#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
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+#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR,val)
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+#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
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+#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR,val)
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+#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
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+#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT,val)
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+#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
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+#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT,val)
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+#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
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+#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY,val)
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+#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
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+#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY,val)
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+#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
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