|
|
@@ -258,3 +258,177 @@
|
|
|
#define OMAP5XXX_CONTROL_STATUS 0x134
|
|
|
#define OMAP5_DEVICETYPE_MASK (0x7 << 6)
|
|
|
|
|
|
+/*
|
|
|
+ * REVISIT: This list of registers is not comprehensive - there are more
|
|
|
+ * that should be added.
|
|
|
+ */
|
|
|
+
|
|
|
+/*
|
|
|
+ * Control module register bit defines - these should eventually go into
|
|
|
+ * their own regbits file. Some of these will be complicated, depending
|
|
|
+ * on the device type (general-purpose, emulator, test, secure, bad, other)
|
|
|
+ * and the security mode (secure, non-secure, don't care)
|
|
|
+ */
|
|
|
+/* CONTROL_DEVCONF0 bits */
|
|
|
+#define OMAP2_MMCSDIO1ADPCLKISEL (1 << 24) /* MMC1 loop back clock */
|
|
|
+#define OMAP24XX_USBSTANDBYCTRL (1 << 15)
|
|
|
+#define OMAP2_MCBSP2_CLKS_MASK (1 << 6)
|
|
|
+#define OMAP2_MCBSP1_FSR_MASK (1 << 4)
|
|
|
+#define OMAP2_MCBSP1_CLKR_MASK (1 << 3)
|
|
|
+#define OMAP2_MCBSP1_CLKS_MASK (1 << 2)
|
|
|
+
|
|
|
+/* CONTROL_DEVCONF1 bits */
|
|
|
+#define OMAP243X_MMC1_ACTIVE_OVERWRITE (1 << 31)
|
|
|
+#define OMAP2_MMCSDIO2ADPCLKISEL (1 << 6) /* MMC2 loop back clock */
|
|
|
+#define OMAP2_MCBSP5_CLKS_MASK (1 << 4) /* > 242x */
|
|
|
+#define OMAP2_MCBSP4_CLKS_MASK (1 << 2) /* > 242x */
|
|
|
+#define OMAP2_MCBSP3_CLKS_MASK (1 << 0) /* > 242x */
|
|
|
+
|
|
|
+/* CONTROL_STATUS bits */
|
|
|
+#define OMAP2_DEVICETYPE_MASK (0x7 << 8)
|
|
|
+#define OMAP2_SYSBOOT_5_MASK (1 << 5)
|
|
|
+#define OMAP2_SYSBOOT_4_MASK (1 << 4)
|
|
|
+#define OMAP2_SYSBOOT_3_MASK (1 << 3)
|
|
|
+#define OMAP2_SYSBOOT_2_MASK (1 << 2)
|
|
|
+#define OMAP2_SYSBOOT_1_MASK (1 << 1)
|
|
|
+#define OMAP2_SYSBOOT_0_MASK (1 << 0)
|
|
|
+
|
|
|
+/* CONTROL_PBIAS_LITE bits */
|
|
|
+#define OMAP343X_PBIASLITESUPPLY_HIGH1 (1 << 15)
|
|
|
+#define OMAP343X_PBIASLITEVMODEERROR1 (1 << 11)
|
|
|
+#define OMAP343X_PBIASSPEEDCTRL1 (1 << 10)
|
|
|
+#define OMAP343X_PBIASLITEPWRDNZ1 (1 << 9)
|
|
|
+#define OMAP343X_PBIASLITEVMODE1 (1 << 8)
|
|
|
+#define OMAP343X_PBIASLITESUPPLY_HIGH0 (1 << 7)
|
|
|
+#define OMAP343X_PBIASLITEVMODEERROR0 (1 << 3)
|
|
|
+#define OMAP2_PBIASSPEEDCTRL0 (1 << 2)
|
|
|
+#define OMAP2_PBIASLITEPWRDNZ0 (1 << 1)
|
|
|
+#define OMAP2_PBIASLITEVMODE0 (1 << 0)
|
|
|
+
|
|
|
+/* CONTROL_PROG_IO1 bits */
|
|
|
+#define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20)
|
|
|
+
|
|
|
+/* CONTROL_IVA2_BOOTMOD bits */
|
|
|
+#define OMAP3_IVA2_BOOTMOD_SHIFT 0
|
|
|
+#define OMAP3_IVA2_BOOTMOD_MASK (0xf << 0)
|
|
|
+#define OMAP3_IVA2_BOOTMOD_IDLE (0x1 << 0)
|
|
|
+
|
|
|
+/* CONTROL_PADCONF_X bits */
|
|
|
+#define OMAP3_PADCONF_WAKEUPEVENT0 (1 << 15)
|
|
|
+#define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14)
|
|
|
+
|
|
|
+#define OMAP343X_SCRATCHPAD_ROM (OMAP343X_CTRL_BASE + 0x860)
|
|
|
+#define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910)
|
|
|
+#define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C
|
|
|
+#define OMAP343X_SCRATCHPAD_REGADDR(reg) OMAP2_L4_IO_ADDRESS(\
|
|
|
+ OMAP343X_SCRATCHPAD + reg)
|
|
|
+
|
|
|
+/* AM35XX_CONTROL_IPSS_CLK_CTRL bits */
|
|
|
+#define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0
|
|
|
+#define AM35XX_CPGMAC_VBUSP_CLK_SHIFT 1
|
|
|
+#define AM35XX_VPFE_VBUSP_CLK_SHIFT 2
|
|
|
+#define AM35XX_HECC_VBUSP_CLK_SHIFT 3
|
|
|
+#define AM35XX_USBOTG_FCLK_SHIFT 8
|
|
|
+#define AM35XX_CPGMAC_FCLK_SHIFT 9
|
|
|
+#define AM35XX_VPFE_FCLK_SHIFT 10
|
|
|
+
|
|
|
+/* AM35XX CONTROL_LVL_INTR_CLEAR bits */
|
|
|
+#define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0)
|
|
|
+#define AM35XX_CPGMAC_C0_RX_PULSE_CLR BIT(1)
|
|
|
+#define AM35XX_CPGMAC_C0_RX_THRESH_CLR BIT(2)
|
|
|
+#define AM35XX_CPGMAC_C0_TX_PULSE_CLR BIT(3)
|
|
|
+#define AM35XX_USBOTGSS_INT_CLR BIT(4)
|
|
|
+#define AM35XX_VPFE_CCDC_VD0_INT_CLR BIT(5)
|
|
|
+#define AM35XX_VPFE_CCDC_VD1_INT_CLR BIT(6)
|
|
|
+#define AM35XX_VPFE_CCDC_VD2_INT_CLR BIT(7)
|
|
|
+
|
|
|
+/* AM35XX CONTROL_IP_SW_RESET bits */
|
|
|
+#define AM35XX_USBOTGSS_SW_RST BIT(0)
|
|
|
+#define AM35XX_CPGMACSS_SW_RST BIT(1)
|
|
|
+#define AM35XX_VPFE_VBUSP_SW_RST BIT(2)
|
|
|
+#define AM35XX_HECC_SW_RST BIT(3)
|
|
|
+#define AM35XX_VPFE_PCLK_SW_RST BIT(4)
|
|
|
+
|
|
|
+/* AM33XX CONTROL_STATUS register */
|
|
|
+#define AM33XX_CONTROL_STATUS 0x040
|
|
|
+#define AM33XX_CONTROL_SEC_CLK_CTRL 0x1bc
|
|
|
+
|
|
|
+/* AM33XX CONTROL_STATUS bitfields (partial) */
|
|
|
+#define AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT 22
|
|
|
+#define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH 0x2
|
|
|
+#define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK (0x3 << 22)
|
|
|
+
|
|
|
+/* CONTROL OMAP STATUS register to identify OMAP3 features */
|
|
|
+#define OMAP3_CONTROL_OMAP_STATUS 0x044c
|
|
|
+
|
|
|
+#define OMAP3_SGX_SHIFT 13
|
|
|
+#define OMAP3_SGX_MASK (3 << OMAP3_SGX_SHIFT)
|
|
|
+#define FEAT_SGX_FULL 0
|
|
|
+#define FEAT_SGX_HALF 1
|
|
|
+#define FEAT_SGX_NONE 2
|
|
|
+
|
|
|
+#define OMAP3_IVA_SHIFT 12
|
|
|
+#define OMAP3_IVA_MASK (1 << OMAP3_IVA_SHIFT)
|
|
|
+#define FEAT_IVA 0
|
|
|
+#define FEAT_IVA_NONE 1
|
|
|
+
|
|
|
+#define OMAP3_L2CACHE_SHIFT 10
|
|
|
+#define OMAP3_L2CACHE_MASK (3 << OMAP3_L2CACHE_SHIFT)
|
|
|
+#define FEAT_L2CACHE_NONE 0
|
|
|
+#define FEAT_L2CACHE_64KB 1
|
|
|
+#define FEAT_L2CACHE_128KB 2
|
|
|
+#define FEAT_L2CACHE_256KB 3
|
|
|
+
|
|
|
+#define OMAP3_ISP_SHIFT 5
|
|
|
+#define OMAP3_ISP_MASK (1 << OMAP3_ISP_SHIFT)
|
|
|
+#define FEAT_ISP 0
|
|
|
+#define FEAT_ISP_NONE 1
|
|
|
+
|
|
|
+#define OMAP3_NEON_SHIFT 4
|
|
|
+#define OMAP3_NEON_MASK (1 << OMAP3_NEON_SHIFT)
|
|
|
+#define FEAT_NEON 0
|
|
|
+#define FEAT_NEON_NONE 1
|
|
|
+
|
|
|
+
|
|
|
+#ifndef __ASSEMBLY__
|
|
|
+#ifdef CONFIG_ARCH_OMAP2PLUS
|
|
|
+extern void __iomem *omap_ctrl_base_get(void);
|
|
|
+extern u8 omap_ctrl_readb(u16 offset);
|
|
|
+extern u16 omap_ctrl_readw(u16 offset);
|
|
|
+extern u32 omap_ctrl_readl(u16 offset);
|
|
|
+extern u32 omap4_ctrl_pad_readl(u16 offset);
|
|
|
+extern void omap_ctrl_writeb(u8 val, u16 offset);
|
|
|
+extern void omap_ctrl_writew(u16 val, u16 offset);
|
|
|
+extern void omap_ctrl_writel(u32 val, u16 offset);
|
|
|
+extern void omap4_ctrl_pad_writel(u32 val, u16 offset);
|
|
|
+
|
|
|
+extern void omap3_save_scratchpad_contents(void);
|
|
|
+extern void omap3_clear_scratchpad_contents(void);
|
|
|
+extern void omap3_restore(void);
|
|
|
+extern void omap3_restore_es3(void);
|
|
|
+extern void omap3_restore_3630(void);
|
|
|
+extern u32 omap3_arm_context[128];
|
|
|
+extern void omap3_control_save_context(void);
|
|
|
+extern void omap3_control_restore_context(void);
|
|
|
+extern void omap3_ctrl_write_boot_mode(u8 bootmode);
|
|
|
+extern void omap_ctrl_write_dsp_boot_addr(u32 bootaddr);
|
|
|
+extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode);
|
|
|
+extern void omap3630_ctrl_disable_rta(void);
|
|
|
+extern int omap3_ctrl_save_padconf(void);
|
|
|
+extern void omap2_set_globals_control(void __iomem *ctrl,
|
|
|
+ void __iomem *ctrl_pad);
|
|
|
+#else
|
|
|
+#define omap_ctrl_base_get() 0
|
|
|
+#define omap_ctrl_readb(x) 0
|
|
|
+#define omap_ctrl_readw(x) 0
|
|
|
+#define omap_ctrl_readl(x) 0
|
|
|
+#define omap4_ctrl_pad_readl(x) 0
|
|
|
+#define omap_ctrl_writeb(x, y) WARN_ON(1)
|
|
|
+#define omap_ctrl_writew(x, y) WARN_ON(1)
|
|
|
+#define omap_ctrl_writel(x, y) WARN_ON(1)
|
|
|
+#define omap4_ctrl_pad_writel(x, y) WARN_ON(1)
|
|
|
+#endif
|
|
|
+#endif /* __ASSEMBLY__ */
|
|
|
+
|
|
|
+#endif /* __ARCH_ARM_MACH_OMAP2_CONTROL_H */
|
|
|
+
|
袁明明