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+/*
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+ * Copyright 2005-2008 Analog Devices Inc.
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+ *
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+ * Licensed under the GPL-2 or later.
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+ */
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+
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+#ifndef _CDEF_LPBLACKFIN_H
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+#define _CDEF_LPBLACKFIN_H
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+
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+/*#if !defined(__ADSPLPBLACKFIN__)
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+#warning cdef_LPBlackfin.h should only be included for 532 compatible chips.
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+#endif
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+*/
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+#include <asm/def_LPBlackfin.h>
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+
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+/*Cache & SRAM Memory*/
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+#define bfin_read_SRAM_BASE_ADDRESS() bfin_read32(SRAM_BASE_ADDRESS)
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+#define bfin_write_SRAM_BASE_ADDRESS(val) bfin_write32(SRAM_BASE_ADDRESS,val)
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+#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
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+#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL,val)
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+#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS)
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+#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS,val)
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+#define bfin_read_DCPLB_FAULT_ADDR() bfin_read32(DCPLB_FAULT_ADDR)
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+#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_write32(DCPLB_FAULT_ADDR,val)
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+/*
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+#define MMR_TIMEOUT 0xFFE00010
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+*/
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+#define bfin_read_DCPLB_ADDR0() bfin_read32(DCPLB_ADDR0)
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+#define bfin_write_DCPLB_ADDR0(val) bfin_write32(DCPLB_ADDR0,val)
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+#define bfin_read_DCPLB_ADDR1() bfin_read32(DCPLB_ADDR1)
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+#define bfin_write_DCPLB_ADDR1(val) bfin_write32(DCPLB_ADDR1,val)
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+#define bfin_read_DCPLB_ADDR2() bfin_read32(DCPLB_ADDR2)
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+#define bfin_write_DCPLB_ADDR2(val) bfin_write32(DCPLB_ADDR2,val)
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+#define bfin_read_DCPLB_ADDR3() bfin_read32(DCPLB_ADDR3)
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+#define bfin_write_DCPLB_ADDR3(val) bfin_write32(DCPLB_ADDR3,val)
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+#define bfin_read_DCPLB_ADDR4() bfin_read32(DCPLB_ADDR4)
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+#define bfin_write_DCPLB_ADDR4(val) bfin_write32(DCPLB_ADDR4,val)
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+#define bfin_read_DCPLB_ADDR5() bfin_read32(DCPLB_ADDR5)
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+#define bfin_write_DCPLB_ADDR5(val) bfin_write32(DCPLB_ADDR5,val)
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+#define bfin_read_DCPLB_ADDR6() bfin_read32(DCPLB_ADDR6)
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+#define bfin_write_DCPLB_ADDR6(val) bfin_write32(DCPLB_ADDR6,val)
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+#define bfin_read_DCPLB_ADDR7() bfin_read32(DCPLB_ADDR7)
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+#define bfin_write_DCPLB_ADDR7(val) bfin_write32(DCPLB_ADDR7,val)
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+#define bfin_read_DCPLB_ADDR8() bfin_read32(DCPLB_ADDR8)
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+#define bfin_write_DCPLB_ADDR8(val) bfin_write32(DCPLB_ADDR8,val)
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+#define bfin_read_DCPLB_ADDR9() bfin_read32(DCPLB_ADDR9)
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+#define bfin_write_DCPLB_ADDR9(val) bfin_write32(DCPLB_ADDR9,val)
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+#define bfin_read_DCPLB_ADDR10() bfin_read32(DCPLB_ADDR10)
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+#define bfin_write_DCPLB_ADDR10(val) bfin_write32(DCPLB_ADDR10,val)
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+#define bfin_read_DCPLB_ADDR11() bfin_read32(DCPLB_ADDR11)
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+#define bfin_write_DCPLB_ADDR11(val) bfin_write32(DCPLB_ADDR11,val)
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+#define bfin_read_DCPLB_ADDR12() bfin_read32(DCPLB_ADDR12)
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+#define bfin_write_DCPLB_ADDR12(val) bfin_write32(DCPLB_ADDR12,val)
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+#define bfin_read_DCPLB_ADDR13() bfin_read32(DCPLB_ADDR13)
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+#define bfin_write_DCPLB_ADDR13(val) bfin_write32(DCPLB_ADDR13,val)
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+#define bfin_read_DCPLB_ADDR14() bfin_read32(DCPLB_ADDR14)
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+#define bfin_write_DCPLB_ADDR14(val) bfin_write32(DCPLB_ADDR14,val)
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+#define bfin_read_DCPLB_ADDR15() bfin_read32(DCPLB_ADDR15)
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+#define bfin_write_DCPLB_ADDR15(val) bfin_write32(DCPLB_ADDR15,val)
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+#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0)
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+#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0,val)
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+#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1)
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+#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1,val)
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+#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2)
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+#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2,val)
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+#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3)
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+#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3,val)
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+#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4)
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+#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4,val)
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+#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5)
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+#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5,val)
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+#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6)
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+#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6,val)
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+#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7)
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+#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7,val)
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+#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8)
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+#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8,val)
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+#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9)
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+#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9,val)
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+#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10)
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+#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10,val)
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+#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11)
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+#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11,val)
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+#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12)
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+#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12,val)
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+#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13)
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+#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13,val)
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+#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14)
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+#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14,val)
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+#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15)
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+#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15,val)
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+#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND)
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+#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND,val)
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+/*
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+#define DTEST_INDEX 0xFFE00304
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+*/
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+#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0)
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+#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0,val)
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+#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1)
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+#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1,val)
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+/*
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+#define DTEST_DATA2 0xFFE00408
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+#define DTEST_DATA3 0xFFE0040C
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+*/
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+#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
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+#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL,val)
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+#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS)
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+#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS,val)
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