|  | @@ -1345,3 +1345,159 @@ static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
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				|  |  |  	.prcm		= {
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				|  |  |  		.omap2 = {
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				|  |  |  			.prcm_reg_id = 1,
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				|  |  | +			.module_bit = OMAP3430_EN_MCBSP3_SHIFT,
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				|  |  | +			.module_offs = OMAP3430_PER_MOD,
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				|  |  | +			.idlest_reg_id = 1,
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				|  |  | +			.idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
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				|  |  | +		},
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				|  |  | +	},
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				|  |  | +};
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				|  |  | +
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				|  |  | +/* SR common */
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				|  |  | +static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
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				|  |  | +	.clkact_shift	= 20,
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				|  |  | +};
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				|  |  | +
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				|  |  | +static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
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				|  |  | +	.sysc_offs	= 0x24,
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				|  |  | +	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
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				|  |  | +	.clockact	= CLOCKACT_TEST_ICLK,
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				|  |  | +	.sysc_fields	= &omap34xx_sr_sysc_fields,
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				|  |  | +};
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				|  |  | +
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				|  |  | +static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
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				|  |  | +	.name = "smartreflex",
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				|  |  | +	.sysc = &omap34xx_sr_sysc,
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				|  |  | +	.rev  = 1,
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				|  |  | +};
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				|  |  | +
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				|  |  | +static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
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				|  |  | +	.sidle_shift	= 24,
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				|  |  | +	.enwkup_shift	= 26,
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				|  |  | +};
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				|  |  | +
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				|  |  | +static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
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				|  |  | +	.sysc_offs	= 0x38,
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				|  |  | +	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
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				|  |  | +	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
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				|  |  | +			SYSC_NO_CACHE),
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				|  |  | +	.sysc_fields	= &omap36xx_sr_sysc_fields,
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				|  |  | +};
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				|  |  | +
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				|  |  | +static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
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				|  |  | +	.name = "smartreflex",
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				|  |  | +	.sysc = &omap36xx_sr_sysc,
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				|  |  | +	.rev  = 2,
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				|  |  | +};
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				|  |  | +
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				|  |  | +/* SR1 */
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				|  |  | +static struct omap_smartreflex_dev_attr sr1_dev_attr = {
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				|  |  | +	.sensor_voltdm_name   = "mpu_iva",
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				|  |  | +};
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				|  |  | +
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				|  |  | +static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
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				|  |  | +	{ .irq = 18 + OMAP_INTC_START, },
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				|  |  | +	{ .irq = -1 },
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				|  |  | +};
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				|  |  | +
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				|  |  | +static struct omap_hwmod omap34xx_sr1_hwmod = {
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				|  |  | +	.name		= "smartreflex_mpu_iva",
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				|  |  | +	.class		= &omap34xx_smartreflex_hwmod_class,
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				|  |  | +	.main_clk	= "sr1_fck",
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				|  |  | +	.prcm		= {
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				|  |  | +		.omap2 = {
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				|  |  | +			.prcm_reg_id = 1,
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				|  |  | +			.module_bit = OMAP3430_EN_SR1_SHIFT,
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				|  |  | +			.module_offs = WKUP_MOD,
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				|  |  | +			.idlest_reg_id = 1,
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				|  |  | +			.idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
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				|  |  | +		},
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				|  |  | +	},
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				|  |  | +	.dev_attr	= &sr1_dev_attr,
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				|  |  | +	.mpu_irqs	= omap3_smartreflex_mpu_irqs,
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				|  |  | +	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
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				|  |  | +};
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				|  |  | +
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				|  |  | +static struct omap_hwmod omap36xx_sr1_hwmod = {
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				|  |  | +	.name		= "smartreflex_mpu_iva",
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				|  |  | +	.class		= &omap36xx_smartreflex_hwmod_class,
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				|  |  | +	.main_clk	= "sr1_fck",
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				|  |  | +	.prcm		= {
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				|  |  | +		.omap2 = {
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				|  |  | +			.prcm_reg_id = 1,
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				|  |  | +			.module_bit = OMAP3430_EN_SR1_SHIFT,
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				|  |  | +			.module_offs = WKUP_MOD,
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				|  |  | +			.idlest_reg_id = 1,
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				|  |  | +			.idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
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				|  |  | +		},
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				|  |  | +	},
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				|  |  | +	.dev_attr	= &sr1_dev_attr,
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				|  |  | +	.mpu_irqs	= omap3_smartreflex_mpu_irqs,
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				|  |  | +};
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				|  |  | +
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				|  |  | +/* SR2 */
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				|  |  | +static struct omap_smartreflex_dev_attr sr2_dev_attr = {
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				|  |  | +	.sensor_voltdm_name	= "core",
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				|  |  | +};
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				|  |  | +
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				|  |  | +static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
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				|  |  | +	{ .irq = 19 + OMAP_INTC_START, },
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				|  |  | +	{ .irq = -1 },
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				|  |  | +};
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				|  |  | +
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				|  |  | +static struct omap_hwmod omap34xx_sr2_hwmod = {
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				|  |  | +	.name		= "smartreflex_core",
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				|  |  | +	.class		= &omap34xx_smartreflex_hwmod_class,
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				|  |  | +	.main_clk	= "sr2_fck",
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				|  |  | +	.prcm		= {
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				|  |  | +		.omap2 = {
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				|  |  | +			.prcm_reg_id = 1,
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				|  |  | +			.module_bit = OMAP3430_EN_SR2_SHIFT,
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				|  |  | +			.module_offs = WKUP_MOD,
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				|  |  | +			.idlest_reg_id = 1,
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				|  |  | +			.idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
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				|  |  | +		},
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				|  |  | +	},
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				|  |  | +	.dev_attr	= &sr2_dev_attr,
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				|  |  | +	.mpu_irqs	= omap3_smartreflex_core_irqs,
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				|  |  | +	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
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				|  |  | +};
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				|  |  | +
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				|  |  | +static struct omap_hwmod omap36xx_sr2_hwmod = {
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				|  |  | +	.name		= "smartreflex_core",
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				|  |  | +	.class		= &omap36xx_smartreflex_hwmod_class,
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				|  |  | +	.main_clk	= "sr2_fck",
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				|  |  | +	.prcm		= {
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				|  |  | +		.omap2 = {
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				|  |  | +			.prcm_reg_id = 1,
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				|  |  | +			.module_bit = OMAP3430_EN_SR2_SHIFT,
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				|  |  | +			.module_offs = WKUP_MOD,
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				|  |  | +			.idlest_reg_id = 1,
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				|  |  | +			.idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
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				|  |  | +		},
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				|  |  | +	},
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				|  |  | +	.dev_attr	= &sr2_dev_attr,
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				|  |  | +	.mpu_irqs	= omap3_smartreflex_core_irqs,
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				|  |  | +};
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				|  |  | +
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				|  |  | +/*
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				|  |  | + * 'mailbox' class
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				|  |  | + * mailbox module allowing communication between the on-chip processors
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				|  |  | + * using a queued mailbox-interrupt mechanism.
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				|  |  | + */
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				|  |  | +
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				|  |  | +static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
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				|  |  | +	.rev_offs	= 0x000,
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				|  |  | +	.sysc_offs	= 0x010,
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				|  |  | +	.syss_offs	= 0x014,
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				|  |  | +	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
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				|  |  | +				SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
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				|  |  | +	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
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				|  |  | +	.sysc_fields	= &omap_hwmod_sysc_type1,
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				|  |  | +};
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				|  |  | +
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				|  |  | +static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
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				|  |  | +	.name = "mailbox",
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				|  |  | +	.sysc = &omap3xxx_mailbox_sysc,
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				|  |  | +};
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				|  |  | +
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