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@@ -2316,3 +2316,65 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
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PORTCR(184, 0xe60520b8), /* PORT184CR */
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PORTCR(184, 0xe60520b8), /* PORT184CR */
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PORTCR(185, 0xe60520b9), /* PORT185CR */
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PORTCR(185, 0xe60520b9), /* PORT185CR */
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PORTCR(186, 0xe60520ba), /* PORT186CR */
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PORTCR(186, 0xe60520ba), /* PORT186CR */
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+ PORTCR(187, 0xe60520bb), /* PORT187CR */
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+ PORTCR(188, 0xe60520bc), /* PORT188CR */
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+ PORTCR(189, 0xe60520bd), /* PORT189CR */
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+ PORTCR(190, 0xe60520be), /* PORT190CR */
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+ PORTCR(191, 0xe60520bf), /* PORT191CR */
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+ PORTCR(192, 0xe60520c0), /* PORT192CR */
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+ PORTCR(193, 0xe60520c1), /* PORT193CR */
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+ PORTCR(194, 0xe60520c2), /* PORT194CR */
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+ PORTCR(195, 0xe60520c3), /* PORT195CR */
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+ PORTCR(196, 0xe60520c4), /* PORT196CR */
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+ PORTCR(197, 0xe60520c5), /* PORT197CR */
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+ PORTCR(198, 0xe60520c6), /* PORT198CR */
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+ PORTCR(199, 0xe60520c7), /* PORT199CR */
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+ PORTCR(200, 0xe60520c8), /* PORT200CR */
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+ PORTCR(201, 0xe60520c9), /* PORT201CR */
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+ PORTCR(202, 0xe60520ca), /* PORT202CR */
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+ PORTCR(203, 0xe60520cb), /* PORT203CR */
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+ PORTCR(204, 0xe60520cc), /* PORT204CR */
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+ PORTCR(205, 0xe60520cd), /* PORT205CR */
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+ PORTCR(206, 0xe60520ce), /* PORT206CR */
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+ PORTCR(207, 0xe60520cf), /* PORT207CR */
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+ PORTCR(208, 0xe60520d0), /* PORT208CR */
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+ PORTCR(209, 0xe60520d1), /* PORT209CR */
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+
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+ PORTCR(210, 0xe60530d2), /* PORT210CR */
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+ PORTCR(211, 0xe60530d3), /* PORT211CR */
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+
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+ { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) {
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+ MSEL1CR_31_0, MSEL1CR_31_1,
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+ MSEL1CR_30_0, MSEL1CR_30_1,
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+ MSEL1CR_29_0, MSEL1CR_29_1,
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+ MSEL1CR_28_0, MSEL1CR_28_1,
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+ MSEL1CR_27_0, MSEL1CR_27_1,
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+ MSEL1CR_26_0, MSEL1CR_26_1,
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+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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+ 0, 0, 0, 0, 0, 0, 0, 0,
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+ MSEL1CR_16_0, MSEL1CR_16_1,
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+ MSEL1CR_15_0, MSEL1CR_15_1,
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+ MSEL1CR_14_0, MSEL1CR_14_1,
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+ MSEL1CR_13_0, MSEL1CR_13_1,
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+ MSEL1CR_12_0, MSEL1CR_12_1,
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+ 0, 0, 0, 0,
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+ MSEL1CR_9_0, MSEL1CR_9_1,
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+ 0, 0,
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+ MSEL1CR_7_0, MSEL1CR_7_1,
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+ MSEL1CR_6_0, MSEL1CR_6_1,
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+ MSEL1CR_5_0, MSEL1CR_5_1,
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+ MSEL1CR_4_0, MSEL1CR_4_1,
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+ MSEL1CR_3_0, MSEL1CR_3_1,
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+ MSEL1CR_2_0, MSEL1CR_2_1,
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+ 0, 0,
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+ MSEL1CR_0_0, MSEL1CR_0_1,
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+ }
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+ },
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+ { PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1) {
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+ 0, 0, 0, 0, 0, 0, 0, 0,
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+ 0, 0, 0, 0, 0, 0, 0, 0,
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+ 0, 0, 0, 0, 0, 0, 0, 0,
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+ 0, 0, 0, 0, 0, 0, 0, 0,
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+ MSEL3CR_15_0, MSEL3CR_15_1,
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+ 0, 0, 0, 0, 0, 0, 0, 0,
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+ 0, 0, 0, 0, 0, 0, 0, 0,
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